23 lines
584 B
VHDL
23 lines
584 B
VHDL
entity core is
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generic (
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HART_ID : natural;
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RESET_VECTOR : yarm_word := (others => '0')
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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-- little-endian memory interface, 4 byte address alignment
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MEM_addr : out yarm_word;
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MEM_read : out std_logic;
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MEM_write : out std_logic;
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MEM_ready : in std_logic;
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MEM_byte_enable : out std_logic_vector(3 downto 0);
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MEM_data_read : in yarm_word;
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MEM_data_write : out yarm_word;
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external_int : in std_logic;
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timer_int : in std_logic;
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software_int : in std_logic
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);
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end core; |