36 lines
956 B
VHDL
36 lines
956 B
VHDL
entity exception_control is
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port (
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clk : in std_logic;
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fetch_raise_exc : in std_logic;
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fetch_exc_data : in exception_data_t;
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-- synchronous exceptions
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decoder_raise_exc : in std_logic;
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decoder_exc_data : in exception_data_t;
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csr_raise_exc : in std_logic;
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csr_exc_data : in exception_data_t;
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alignment_raise_exc : in std_logic;
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alignment_exc_data : in exception_data_t;
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datamem_raise_exc : in std_logic;
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datamem_exc_data : in exception_data_t;
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-- interrupts
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global_int_enabled : in std_logic;
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interrupts_enabled : in yarm_word;
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interrupts_pending : in yarm_word;
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-- stage inputs for return address + trap value (instruction)
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stage_inputs : in pipeline_frames_t;
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interrupted_stage : in pipeline_stage_t;
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may_interrupt : in std_logic;
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do_trap : out std_logic;
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trap_cause : out yarm_trap_cause;
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trap_address : out yarm_word;
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trap_value : out yarm_word
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);
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end exception_control; |