21 lines
484 B
VHDL
21 lines
484 B
VHDL
entity decoder is
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port (
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clk : in std_logic;
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enable : in std_logic;
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async_addr_rs1 : out register_addr_t;
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async_addr_rs2 : out register_addr_t;
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alu_muxsel_a : out mux_selector_t;
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alu_muxsel_b : out mux_selector_t;
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alu_muxsel_cmp2 : out mux_selector_t;
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csr_muxsel_in : out mux_selector_t;
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instr_info_in : in instruction_info_t;
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instr_info_out : out instruction_info_t;
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raise_exc : out std_logic;
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exc_data : out exception_data_t
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);
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end decoder; |