16 lines
304 B
VHDL
16 lines
304 B
VHDL
entity registers is
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port (
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clk : in std_logic;
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read_enable : in std_logic;
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write_enable : in std_logic;
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addr_a : in register_addr_t;
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addr_b : in register_addr_t;
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addr_d : in register_addr_t;
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data_a : out yarm_word;
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data_b : out yarm_word;
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data_d : in yarm_word
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);
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end registers; |