11 commits

Author	SHA1	Message	Date
Xiretza	79fce1afc1	vhdl: disable test UDP sender	2022-06-05 21:36:10 +02:00
Xiretza	9121ccfdbe	vhdl: implement setting LEDs via UDP	2022-06-05 21:36:10 +02:00
Xiretza	d5b0ee2cfa	vhdl: rename NUM_DRIVERS to NUM_STRANDS	2022-06-05 21:36:10 +02:00
Xiretza	2ec250e79d	vhdl: rename clk_sys to sys_clk	2022-06-05 21:36:10 +02:00
Xiretza	57e6daedcc	vhdl: move ws2812 driver to splink module	2022-06-05 21:36:10 +02:00
Xiretza	01fe200d92	Pixel UDP port demo	2022-06-05 16:35:20 +02:00
Xiretza	ba1aa9181e	vhdl: add ws2812 demo	2022-06-05 13:10:19 +02:00
Xiretza	ffbe87f1f1	Add ws2812 submodule	2022-06-05 10:21:44 +02:00
Xiretza	de6a38044b	vhdl: assert reset if PLL is not locked	2022-06-04 21:53:14 +02:00
Xiretza	d624673804	Add liteeth core	2022-06-04 21:51:28 +02:00
Xiretza	d6687786a7	Add basic tools and VHDL skeleton	2022-06-03 19:11:07 +02:00