8 commits

Author	SHA1	Message	Date
Xiretza	40caa85d92	vhdl: implement multiple strands	2022-06-06 12:58:41 +02:00
Xiretza	24e3b11588	Use little endian byte order in network streams	2022-06-06 10:29:45 +02:00
Xiretza	ccd911dc1e	vhdl: implement feedback packets	2022-06-05 22:56:29 +02:00
Xiretza	d0e65a3126	vhdl: remove unused signals	2022-06-05 22:27:16 +02:00
Xiretza	9121ccfdbe	vhdl: implement setting LEDs via UDP	2022-06-05 21:36:10 +02:00
Xiretza	d5b0ee2cfa	vhdl: rename NUM_DRIVERS to NUM_STRANDS	2022-06-05 21:36:10 +02:00
Xiretza	57e6daedcc	vhdl: move ws2812 driver to splink module	2022-06-05 21:36:10 +02:00
Xiretza	d6687786a7	Add basic tools and VHDL skeleton	2022-06-03 19:11:07 +02:00