21 commits

Author	SHA1	Message	Date
Xiretza	287fa0b7ee	Add info about SoC software	2020-03-30 23:39:46 +02:00
Xiretza	f4164ca3f2	Add info stub for SoC UART	2020-03-30 23:38:24 +02:00
Xiretza	637573fd43	Update core diagram	2020-03-30 23:38:10 +02:00
Xiretza	c15a3ec470	Improve phrasing	2020-03-30 20:56:18 +02:00
Xiretza	3e66e5d6c8	Add info about external bus clock speed	2020-03-30 20:55:43 +02:00
Xiretza	e86df5b9ba	Link to VHDL intro appendix	2020-03-30 20:54:36 +02:00
Xiretza	59299f196c	Cite VHDL's strong typing	2020-03-30 20:54:17 +02:00
Xiretza	1eaddf7d3d	Rework heading hierarchy	2020-03-30 15:20:53 +02:00
Xiretza	103a8e3d19	Turn VHDL introduction into appendix	2020-03-30 15:18:16 +02:00
Xiretza	3dc6bbf390	Misc fixes and improvements	2020-03-29 22:01:05 +02:00
Xiretza	ffb1fe4060	Add citations for GitLab CI and RISC-V spec	2020-03-29 21:58:14 +02:00
Xiretza	3b65229eae	Add information about formal verification	2020-03-29 19:03:49 +02:00
Xiretza	e891568008	Small fixes	2020-03-29 18:05:21 +02:00
Xiretza	40bc2327fd	Add information about DRAM interface	2020-03-29 18:05:05 +02:00
Xiretza	89f0a1565e	Improve FPGA comparison tables	2020-03-29 18:04:34 +02:00
Xiretza	239106c2fd	Add nbsp before citations	2020-03-29 18:03:16 +02:00
Xiretza	dc77d4bf61	Add labels and captions to listings	2020-03-27 14:20:22 +01:00
Xiretza	ad723217ad	Add information about external bus	2020-03-27 12:50:24 +01:00
Xiretza	244380ee5f	Fix citations, change citation style	2020-03-27 12:49:50 +01:00
Xiretza	e65030ef47	Add information about riscv compliance tests	2020-03-27 12:49:38 +01:00
Xiretza	ed378c0917	Merge batman content	2020-03-23 14:02:38 +01:00