Xiretza 103a8e3d19 Turn VHDL introduction into appendix		2020-03-30 15:18:16 +02:00
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core	Add citations for GitLab CI and RISC-V spec	2020-03-29 21:58:14 +02:00
soc	Misc fixes and improvements	2020-03-29 22:01:05 +02:00
vhdl_intro	Turn VHDL introduction into appendix	2020-03-30 15:18:16 +02:00