Xiretza 637573fd43 Update core diagram		2020-03-30 23:38:10 +02:00
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core	Update core diagram	2020-03-30 23:38:10 +02:00
soc	Improve phrasing	2020-03-30 20:56:18 +02:00
vhdl_intro	Link to VHDL intro appendix	2020-03-30 20:54:36 +02:00