Xiretza 3e66e5d6c8 Add info about external bus clock speed		2020-03-30 20:55:43 +02:00
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core	Rework heading hierarchy	2020-03-30 15:20:53 +02:00
soc	Add info about external bus clock speed	2020-03-30 20:55:43 +02:00
vhdl_intro	Link to VHDL intro appendix	2020-03-30 20:54:36 +02:00