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splink
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6 commits
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Xiretza
01fe200d92
Pixel UDP port demo
2022-06-05 16:35:20 +02:00
Xiretza
ba1aa9181e
vhdl: add ws2812 demo
2022-06-05 13:10:19 +02:00
Xiretza
ffbe87f1f1
Add ws2812 submodule
2022-06-05 10:21:44 +02:00
Xiretza
de6a38044b
vhdl: assert reset if PLL is not locked
2022-06-04 21:53:14 +02:00
Xiretza
d624673804
Add liteeth core
2022-06-04 21:51:28 +02:00
Xiretza
d6687786a7
Add basic tools and VHDL skeleton
2022-06-03 19:11:07 +02:00