Xiretza
3c5c3a4555
liteeth splits the rx data stream into 4-byte chunks and interprets them as little-endian 32-bit vecs; similar for the other direction.
24 lines
633 B
VHDL
24 lines
633 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package util is
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function flip_endianness(val : in std_logic_vector) return std_logic_vector;
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end package;
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package body util is
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function flip_endianness(val : in std_logic_vector) return std_logic_vector is
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constant BYTES : natural := val'length / 8;
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variable ret : std_logic_vector(val'length-1 downto 0);
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begin
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assert val'length mod 8 = 0
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report "length of vector not a multiple of 8"
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severity failure;
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for i in 0 to BYTES-1 loop
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ret((BYTES-i)*8 - 1 downto (BYTES-i-1) * 8) := val((i+1)*8 - 1 downto i*8);
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end loop;
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return ret;
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end function;
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end package body;
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