4 commits

Author	SHA1	Message	Date
Xiretza	ffbe87f1f1	Add ws2812 submodule	2022-06-05 10:21:44 +02:00
Xiretza	de6a38044b	vhdl: assert reset if PLL is not locked	2022-06-04 21:53:14 +02:00
Xiretza	d624673804	Add liteeth core	2022-06-04 21:51:28 +02:00
Xiretza	d6687786a7	Add basic tools and VHDL skeleton	2022-06-03 19:11:07 +02:00