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46 commits 2 branches 0 tags 883 KiB
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5 commits

Author SHA1 Message Date
Xiretza 5f589aca37 Use wishbone interface for CPU port 2022-07-14 16:05:49 +02:00
Xiretza 01fe200d92 Pixel UDP port demo 2022-06-05 16:35:20 +02:00
Xiretza d624673804 Add liteeth core 2022-06-04 21:51:28 +02:00
Xiretza eedf254b15 fix(gen_liteeth): fix configurations 2022-06-03 22:17:13 +02:00
Xiretza d6687786a7 Add basic tools and VHDL skeleton 2022-06-03 19:11:07 +02:00