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Add ws2812 submodule

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Xiretza 2022-06-05 10:21:44 +02:00
parent de6a38044b
commit ffbe87f1f1
3 changed files with 5 additions and 1 deletions
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3
.gitmodules vendored Normal file
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@ -0,0 +1,3 @@
[submodule "vhdl/ws2812_vhdl"]
path = vhdl/ws2812_vhdl
url = https://gitlab.com/xiretza/ws2812_vhdl

2
Makefile
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@ -13,7 +13,7 @@ VHDL_DIR = vhdl
WORKLIB_NAME = splink
VHDL_FILES = $(wildcard $(VHDL_DIR)/*.vhdl)
VHDL_FILES = $(wildcard $(VHDL_DIR)/*.vhdl $(VHDL_DIR)/ws2812_vhdl/*.vhd)
VERILOG_FILES = $(LITEX_WORKDIR)/gateware/liteeth_core.v
SBY_FILES =

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vhdl/ws2812_vhdl Submodule

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Subproject commit 0d1688f1840b8b5894b9f4cd027fcc1653dd3657