diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..e723471
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "vhdl/ws2812_vhdl"]
+	path = vhdl/ws2812_vhdl
+	url = https://gitlab.com/xiretza/ws2812_vhdl
diff --git a/Makefile b/Makefile
index ca0295a..7377677 100644
--- a/Makefile
+++ b/Makefile
@@ -13,7 +13,7 @@ VHDL_DIR  = vhdl
 
 WORKLIB_NAME = splink
 
-VHDL_FILES = $(wildcard $(VHDL_DIR)/*.vhdl)
+VHDL_FILES = $(wildcard $(VHDL_DIR)/*.vhdl $(VHDL_DIR)/ws2812_vhdl/*.vhd)
 VERILOG_FILES = $(LITEX_WORKDIR)/gateware/liteeth_core.v
 SBY_FILES =
 
diff --git a/vhdl/ws2812_vhdl b/vhdl/ws2812_vhdl
new file mode 160000
index 0000000..0d1688f
--- /dev/null
+++ b/vhdl/ws2812_vhdl
@@ -0,0 +1 @@
+Subproject commit 0d1688f1840b8b5894b9f4cd027fcc1653dd3657