From ffbe87f1f16a72b731152f9d5c0a1154e3a85120 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Sun, 5 Jun 2022 10:21:44 +0200 Subject: [PATCH] Add ws2812 submodule --- .gitmodules | 3 +++ Makefile | 2 +- vhdl/ws2812_vhdl | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) create mode 100644 .gitmodules create mode 160000 vhdl/ws2812_vhdl diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..e723471 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "vhdl/ws2812_vhdl"] + path = vhdl/ws2812_vhdl + url = https://gitlab.com/xiretza/ws2812_vhdl diff --git a/Makefile b/Makefile index ca0295a..7377677 100644 --- a/Makefile +++ b/Makefile @@ -13,7 +13,7 @@ VHDL_DIR = vhdl WORKLIB_NAME = splink -VHDL_FILES = $(wildcard $(VHDL_DIR)/*.vhdl) +VHDL_FILES = $(wildcard $(VHDL_DIR)/*.vhdl $(VHDL_DIR)/ws2812_vhdl/*.vhd) VERILOG_FILES = $(LITEX_WORKDIR)/gateware/liteeth_core.v SBY_FILES = diff --git a/vhdl/ws2812_vhdl b/vhdl/ws2812_vhdl new file mode 160000 index 0000000..0d1688f --- /dev/null +++ b/vhdl/ws2812_vhdl @@ -0,0 +1 @@ +Subproject commit 0d1688f1840b8b5894b9f4cd027fcc1653dd3657