Xiretza
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a28816b2e6
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Add patched liteeth.core module to allow hybrid mode
https://github.com/enjoy-digital/liteeth/pull/116
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2022-07-14 16:04:40 +02:00 |
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Xiretza
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bbb3ec5d30
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Use wishbone interface for CPU port
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2022-06-30 18:20:36 +02:00 |
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Xiretza
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01fe200d92
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Pixel UDP port demo
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2022-06-05 16:35:20 +02:00 |
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Xiretza
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d624673804
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Add liteeth core
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2022-06-04 21:51:28 +02:00 |
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Xiretza
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eedf254b15
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fix(gen_liteeth): fix configurations
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2022-06-03 22:17:13 +02:00 |
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Xiretza
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d6687786a7
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Add basic tools and VHDL skeleton
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2022-06-03 19:11:07 +02:00 |
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