3 commits

Author	SHA1	Message	Date
Xiretza	2ec250e79d	vhdl: rename clk_sys to sys_clk	2022-06-05 21:36:10 +02:00
Xiretza	d624673804	Add liteeth core	2022-06-04 21:51:28 +02:00
Xiretza	d6687786a7	Add basic tools and VHDL skeleton	2022-06-03 19:11:07 +02:00