xiretza/splink
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity
48 commits 2 branches 0 tags 883 KiB
Commit graph

3 commits

Author SHA1 Message Date
Xiretza 2ec250e79d vhdl: rename clk_sys to sys_clk 2022-06-05 21:36:10 +02:00
Xiretza d624673804 Add liteeth core 2022-06-04 21:51:28 +02:00
Xiretza d6687786a7 Add basic tools and VHDL skeleton 2022-06-03 19:11:07 +02:00