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Use wishbone interface for CPU port

This commit is contained in:
Xiretza 2022-06-30 18:20:36 +02:00
parent 5fb8d3a176
commit 5f589aca37
2 changed files with 40 additions and 47 deletions
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47
gen_liteeth.py
View File

@ -43,6 +43,9 @@ _io = [
# IP/MAC Address. # IP/MAC Address.
("ip_address", 0, Pins(32)), ("ip_address", 0, Pins(32)),
# Interrupt
("interrupt", 0, Pins(1)),
# MII PHY Pads # MII PHY Pads
("mii_eth_clocks", 0, ("mii_eth_clocks", 0,
Subsignal("tx", Pins(1)), Subsignal("tx", Pins(1)),
@ -180,40 +183,26 @@ class UDPCore(PHYCore):
clk_freq=CLK_FREQ, clk_freq=CLK_FREQ,
dw=8, dw=8,
with_sys_datapath=False, with_sys_datapath=False,
hybrid=True,
) )
# DHCP port # CPU port
data_width = 32 nrxslots = self.core.mac.rx_slots.constant
ntxslots = self.core.mac.tx_slots.constant
platform.add_extension(get_udp_streamer_port_ios( wb_bus = wishbone.Interface()
"dhcp", platform.add_extension(wb_bus.get_ios("wishbone"))
data_width=data_width, self.comb += wb_bus.connect_to_pads(self.platform.request("wishbone"), mode="slave")
)) self.add_wb_master(wb_bus)
dhcp_ios = platform.request("dhcp")
dhcp_streamer = LiteEthUDPStreamer( ethmac_region_size = (nrxslots + ntxslots)*buffer_depth
self.core.udp, ethmac_region = SoCRegion(
ip_address=dhcp_ios.ip_address, origin=self.mem_map.get("ethmac", None),
udp_port=67, size=ethmac_region_size,
data_width=data_width, cached=False
tx_fifo_depth=64,
rx_fifo_depth=64
) )
self.submodules += dhcp_streamer self.bus.add_slave(name="ethmac", slave=self.core.mac.bus, region=ethmac_region)
self.comb += self.platform.request("interrupt").eq(self.core.mac.ev.irq)
self.comb += [
# Connect UDP Sink IOs to UDP Steamer.
dhcp_streamer.sink.valid.eq(dhcp_ios.sink_valid),
dhcp_streamer.sink.last.eq(dhcp_ios.sink_last),
dhcp_ios.sink_ready.eq(dhcp_streamer.sink.ready),
dhcp_streamer.sink.data.eq(dhcp_ios.sink_data),
# Connect UDP Streamer to UDP Source IOs.
dhcp_ios.source_valid.eq(dhcp_streamer.source.valid),
dhcp_ios.source_last.eq(dhcp_streamer.source.last),
dhcp_streamer.source.ready.eq(dhcp_ios.source_ready),
dhcp_ios.source_data.eq(dhcp_streamer.source.data),
]
# Pixel port # Pixel port
data_width = 32 data_width = 32

40
vhdl/arty_a7.vhdl
View File

@ -87,18 +87,19 @@ architecture a of arty_a7 is
ip_address : in std_logic_vector(31 downto 0); ip_address : in std_logic_vector(31 downto 0);
--== DHCP PORT ==-- --== WISHBONE PORT ==--
dhcp_ip_address : in std_logic_vector(31 downto 0); wishbone_adr : in std_logic_vector(29 downto 0);
wishbone_dat_w : in std_logic_vector(31 downto 0);
dhcp_sink_valid : in std_logic; wishbone_dat_r : out std_logic_vector(31 downto 0);
dhcp_sink_last : in std_logic; wishbone_sel : in std_logic_vector(3 downto 0);
dhcp_sink_ready : out std_logic; wishbone_cyc : in std_logic;
dhcp_sink_data : in std_logic_vector(31 downto 0); wishbone_stb : in std_logic;
wishbone_ack : out std_logic;
dhcp_source_valid : out std_logic; wishbone_we : in std_logic;
dhcp_source_last : out std_logic; wishbone_cti : in std_logic_vector(2 downto 0);
dhcp_source_ready : in std_logic; wishbone_bte : in std_logic_vector(1 downto 0);
dhcp_source_data : out std_logic_vector(31 downto 0); wishbone_err : out std_logic;
interrupt : out std_logic;
--== PIXEL DATA PORT ==-- --== PIXEL DATA PORT ==--
pixel_bind_port : in std_logic_vector(15 downto 0); pixel_bind_port : in std_logic_vector(15 downto 0);
@ -247,12 +248,15 @@ begin
ip_address => x"0a141e28", -- 10.20.30.40 ip_address => x"0a141e28", -- 10.20.30.40
dhcp_ip_address => x"0a141e29", -- 10.20.30.41 --== WISHBONE PORT ==--
dhcp_sink_valid => '0', wishbone_adr => (others => '1'),
dhcp_sink_last => '1', wishbone_dat_w => (others => '1'),
dhcp_sink_data => x"cafebebe", wishbone_sel => (others => '1'),
wishbone_cyc => '1',
dhcp_source_ready => '1', wishbone_stb => '1',
wishbone_we => '1',
wishbone_cti => (others => '1'),
wishbone_bte => (others => '1'),
--== PIXEL DATA PORT ==-- --== PIXEL DATA PORT ==--
pixel_bind_port => x"effd", -- port 61437 - "PIXEL" pixel_bind_port => x"effd", -- port 61437 - "PIXEL"