diff --git a/gen_liteeth.py b/gen_liteeth.py
index 898b8cf..45d514f 100755
--- a/gen_liteeth.py
+++ b/gen_liteeth.py
@@ -43,6 +43,9 @@ _io = [
     # IP/MAC Address.
     ("ip_address",  0, Pins(32)),
 
+    # Interrupt
+    ("interrupt", 0, Pins(1)),
+
     # MII PHY Pads
     ("mii_eth_clocks", 0,
         Subsignal("tx", Pins(1)),
@@ -180,40 +183,26 @@ class UDPCore(PHYCore):
             clk_freq=CLK_FREQ,
             dw=8,
             with_sys_datapath=False,
+            hybrid=True,
         )
 
-        # DHCP port
-        data_width = 32
+        # CPU port
+        nrxslots = self.core.mac.rx_slots.constant
+        ntxslots = self.core.mac.tx_slots.constant
 
-        platform.add_extension(get_udp_streamer_port_ios(
-            "dhcp",
-            data_width=data_width,
-        ))
-        dhcp_ios = platform.request("dhcp")
+        wb_bus = wishbone.Interface()
+        platform.add_extension(wb_bus.get_ios("wishbone"))
+        self.comb += wb_bus.connect_to_pads(self.platform.request("wishbone"), mode="slave")
+        self.add_wb_master(wb_bus)
 
-        dhcp_streamer = LiteEthUDPStreamer(
-            self.core.udp,
-            ip_address=dhcp_ios.ip_address,
-            udp_port=67,
-            data_width=data_width,
-            tx_fifo_depth=64,
-            rx_fifo_depth=64
+        ethmac_region_size = (nrxslots + ntxslots)*buffer_depth
+        ethmac_region = SoCRegion(
+            origin=self.mem_map.get("ethmac", None),
+            size=ethmac_region_size,
+            cached=False
         )
-        self.submodules += dhcp_streamer
-
-        self.comb += [
-            # Connect UDP Sink IOs to UDP Steamer.
-            dhcp_streamer.sink.valid.eq(dhcp_ios.sink_valid),
-            dhcp_streamer.sink.last.eq(dhcp_ios.sink_last),
-            dhcp_ios.sink_ready.eq(dhcp_streamer.sink.ready),
-            dhcp_streamer.sink.data.eq(dhcp_ios.sink_data),
-
-            # Connect UDP Streamer to UDP Source IOs.
-            dhcp_ios.source_valid.eq(dhcp_streamer.source.valid),
-            dhcp_ios.source_last.eq(dhcp_streamer.source.last),
-            dhcp_streamer.source.ready.eq(dhcp_ios.source_ready),
-            dhcp_ios.source_data.eq(dhcp_streamer.source.data),
-        ]
+        self.bus.add_slave(name="ethmac", slave=self.core.mac.bus, region=ethmac_region)
+        self.comb += self.platform.request("interrupt").eq(self.core.mac.ev.irq)
 
         # Pixel port
         data_width = 32
diff --git a/vhdl/arty_a7.vhdl b/vhdl/arty_a7.vhdl
index 24a6a46..0e1eaf5 100644
--- a/vhdl/arty_a7.vhdl
+++ b/vhdl/arty_a7.vhdl
@@ -87,18 +87,19 @@ architecture a of arty_a7 is
 
 			ip_address : in std_logic_vector(31 downto 0);
 
-			--== DHCP PORT ==--
-			dhcp_ip_address : in std_logic_vector(31 downto 0);
-
-			dhcp_sink_valid : in std_logic;
-			dhcp_sink_last : in std_logic;
-			dhcp_sink_ready : out std_logic;
-			dhcp_sink_data : in std_logic_vector(31 downto 0);
-
-			dhcp_source_valid : out std_logic;
-			dhcp_source_last : out std_logic;
-			dhcp_source_ready : in std_logic;
-			dhcp_source_data : out std_logic_vector(31 downto 0);
+			--== WISHBONE PORT ==--
+			wishbone_adr : in std_logic_vector(29 downto 0);
+			wishbone_dat_w : in std_logic_vector(31 downto 0);
+			wishbone_dat_r : out std_logic_vector(31 downto 0);
+			wishbone_sel : in std_logic_vector(3 downto 0);
+			wishbone_cyc : in std_logic;
+			wishbone_stb : in std_logic;
+			wishbone_ack : out std_logic;
+			wishbone_we : in std_logic;
+			wishbone_cti : in std_logic_vector(2 downto 0);
+			wishbone_bte : in std_logic_vector(1 downto 0);
+			wishbone_err : out std_logic;
+			interrupt : out std_logic;
 
 			--== PIXEL DATA PORT ==--
 			pixel_bind_port : in std_logic_vector(15 downto 0);
@@ -247,12 +248,15 @@ begin
 
 		ip_address => x"0a141e28", -- 10.20.30.40
 
-		dhcp_ip_address => x"0a141e29", -- 10.20.30.41
-		dhcp_sink_valid => '0',
-		dhcp_sink_last => '1',
-		dhcp_sink_data => x"cafebebe",
-
-		dhcp_source_ready => '1',
+		--== WISHBONE PORT ==--
+		wishbone_adr => (others => '1'),
+		wishbone_dat_w => (others => '1'),
+		wishbone_sel => (others => '1'),
+		wishbone_cyc => '1',
+		wishbone_stb => '1',
+		wishbone_we => '1',
+		wishbone_cti => (others => '1'),
+		wishbone_bte => (others => '1'),
 
 		--== PIXEL DATA PORT ==--
 		pixel_bind_port => x"effd", -- port 61437 - "PIXEL"