Xiretza
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1eaddf7d3d
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Rework heading hierarchy
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2020-03-30 15:20:53 +02:00 |
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Xiretza
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103a8e3d19
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Turn VHDL introduction into appendix
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2020-03-30 15:18:16 +02:00 |
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Xiretza
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ed378c0917
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Merge batman content
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2020-03-23 14:02:38 +01:00 |
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Xiretza
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c4a71b39dd
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Misc updates, add core and SoC docs
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2020-03-01 17:13:51 +01:00 |
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Xiretza
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ae4c533320
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Add bibliography
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2020-02-28 18:35:10 +01:00 |
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Xiretza
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387e9d61c6
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Add initial outline of DS
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2019-12-10 15:32:02 +01:00 |
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Xiretza
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3b360e3237
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Move sample DS
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2019-12-10 14:23:44 +01:00 |
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Xiretza
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b9fa071e76
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Initial import
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2019-09-20 17:32:06 +02:00 |
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