9 commits

Author	SHA1	Message	Date
Xiretza	103a8e3d19	Turn VHDL introduction into appendix	2020-03-30 15:18:16 +02:00
Xiretza	89f0a1565e	Improve FPGA comparison tables	2020-03-29 18:04:34 +02:00
Xiretza	dc77d4bf61	Add labels and captions to listings	2020-03-27 14:20:22 +01:00
Xiretza	244380ee5f	Fix citations, change citation style	2020-03-27 12:49:50 +01:00
Xiretza	ed378c0917	Merge batman content	2020-03-23 14:02:38 +01:00
Xiretza	c4a71b39dd	Misc updates, add core and SoC docs	2020-03-01 17:13:51 +01:00
Xiretza	ae4c533320	Add bibliography	2020-02-28 18:35:10 +01:00
Xiretza	387e9d61c6	Add initial outline of DS	2019-12-10 15:32:02 +01:00
Tyrolyean	35b62c8251	Adeed tex files for dipl ... Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>	2019-09-07 18:15:15 +02:00