8 commits

Author	SHA1	Message	Date
Xiretza	1eaddf7d3d	Rework heading hierarchy	2020-03-30 15:20:53 +02:00
Xiretza	103a8e3d19	Turn VHDL introduction into appendix	2020-03-30 15:18:16 +02:00
Xiretza	ed378c0917	Merge batman content	2020-03-23 14:02:38 +01:00
Xiretza	c4a71b39dd	Misc updates, add core and SoC docs	2020-03-01 17:13:51 +01:00
Xiretza	ae4c533320	Add bibliography	2020-02-28 18:35:10 +01:00
Xiretza	387e9d61c6	Add initial outline of DS	2019-12-10 15:32:02 +01:00
Xiretza	3b360e3237	Move sample DS	2019-12-10 14:23:44 +01:00
Xiretza	b9fa071e76	Initial import	2019-09-20 17:32:06 +02:00