FINAL COMMIT

This commit concludes the development phase of this thesis as the deadline set
in 10 hours from now comes closer and closer and I want to sleep at one point
as well. Probably not gonna be awake until then. Either this is going out well
one way or the other we will see... FUCK COMMIT MESSAGES!

Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
This commit is contained in:
Tyrolyean 2020-04-01 02:37:52 +02:00
parent 9fadf57f82
commit d620d39bdf
No known key found for this signature in database
GPG key ID: 81EC9BAC5E9667C6
9 changed files with 94 additions and 7 deletions

View file

@ -207,6 +207,13 @@
author = {Unknown Author}, author = {Unknown Author},
url = {https://www.nxp.com/docs/en/user-guide/UM10204.pdf} url = {https://www.nxp.com/docs/en/user-guide/UM10204.pdf}
} }
@book{boehmer,
year = {2009},
month = Aug,
title = {Elemente der angewandten Elektronik},
publisher = {Viehweg},
author = {Erwin Böhmer, Dietmar Erhardt, Wolfgang Oberschlep}
}
@Manual{ddc, @Manual{ddc,
year = {2007}, year = {2007},
month = Dec, month = Dec,

BIN
main.pdf (Stored with Git LFS)

Binary file not shown.

View file

@ -190,6 +190,7 @@ geschlechtsunabh"angig verstanden werden soll.
\allAuth\input{sections/Anhang/Projektterminplanung/projektterminplanung.tex} \allAuth\input{sections/Anhang/Projektterminplanung/projektterminplanung.tex}
\allAuth\input{sections/Anhang/flash.tex} \allAuth\input{sections/Anhang/flash.tex}
\DP\input{sections/Anhang/qualitaetssicherung.tex}
\AB\subfile{sections/vhdl_intro/vhdl_intro.tex} \AB\subfile{sections/vhdl_intro/vhdl_intro.tex}
\end{appendices} \end{appendices}

View file

@ -63,11 +63,11 @@ Table \ref{tab:brauns_work} shows the times worked.
\textbf{Date} & \textbf{Duration [h]} & \textbf{Task}\\ \textbf{Date} & \textbf{Duration [h]} & \textbf{Task}\\
\hline \hline
\hline \hline
2018-12-11 & 3 & Create Quartus project, implement first proof-of-concept design \\ 2018-12-11 & 3 & Cimplement first proof-of-concept design \\
\hline \hline
2018-12-19 & 3 & ALU design and corresponding test bench \\ 2018-12-19 & 3 & ALU design and corresponding test bench \\
\hline \hline
2019-01-18 & 5 & First processor prototype capable of running programs \\ 2019-01-18 & 5 & First processor prototype \\
\hline \hline
2019-01-20 & 2 & Preliminary firmware build system \\ 2019-01-20 & 2 & Preliminary firmware build system \\
\hline \hline
@ -109,7 +109,7 @@ Table \ref{tab:brauns_work} shows the times worked.
\hline \hline
2019-03-04 & 1 & Misc bug fixes \\ 2019-03-04 & 1 & Misc bug fixes \\
\hline \hline
2019-03-10 & 2 & Diagnose and fix interrupt related processor bug \\ 2019-03-10 & 2 & Fix interrupt related processor bug \\
\hline \hline
2019-03-11 & 3 & CSR illegal instruction exceptions \\ 2019-03-11 & 3 & CSR illegal instruction exceptions \\
\hline \hline
@ -246,7 +246,7 @@ Table \ref{tab:brauns_work} shows the times worked.
2020-03-31 & 4 & Documentation \\ 2020-03-31 & 4 & Documentation \\
\hline \hline
\hline \hline
2020-04-01 & \textbf{SUM during school year} & 150h\\ \multicolumn{2}{c}{\textbf{SUM during school year}} & 150h\\
\hline \hline
\caption{Work time reference - Brauns} \caption{Work time reference - Brauns}
\label{tab:brauns_work} \label{tab:brauns_work}

View file

@ -38,7 +38,7 @@ Plank respectively.
\textbf{Directory} & \textbf{Contents}\\ \textbf{Directory} & \textbf{Contents}\\
\hline \hline
\hline \hline
code & Code sampkes written for this thesis\\ code & Code samples written for this thesis\\
\hline \hline
dipl & The source code for this thesis in \LaTeX\\ dipl & The source code for this thesis in \LaTeX\\
\hline \hline

View file

@ -0,0 +1,32 @@
\section{Qualitätssicherung nach ISO-9003}
Im zuge der Qualitätssicherung nach ISO-9003 wurden für die Hardwareperipherie
laufend Messungen zur Funktionsprüfungen durchgeführt sowie für den Prozessor
diverse Simulationsmodelle erstellt und verwendet. Der Messverlauf wurde
beschrieben und die Messungen mit dem Soll-Wert verglichen. Zur Verifikation
der in MS1 gesammelten PDF-Dateien wurde ein Shell-Skript verfasst, welches
in Listing \ref{lst:mst-t1} eingesehen werden kann. Die Tests verifizieren nach
dem Grobdesign welches in der Abgabe zu Meilenstein 1 auf dem dieser
Diplomarbeit beigelegten Datenträger eingesehen werden kann.
\begin{lstlisting}[language=bash,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:mst-t1},
caption={Shell-Skript zum Testen der PDF-Dokumente},
columns=flexible]
#!/bin/bash
for f in *.pdf; do
echo "########################################"
echo "Tesing $f..."
echo "########################################" >> ./logfile
if pdfinfo "$f" >> ./logfile; then
echo "$f is correct!"
else
echo "$f is broken!"
fi
echo "########################################"
done
\end{lstlisting}

View file

@ -20,6 +20,9 @@ DAC was developed for audio aplications\cite{tlc7528}, which made its use
obvious. The TLC-7528 was the only IC available as DIP obvious. The TLC-7528 was the only IC available as DIP
\footnote{DIP... Dual Inline Package}, of which the pinout can be seen in Figure \footnote{DIP... Dual Inline Package}, of which the pinout can be seen in Figure
\ref{fig:tlc7528_pinout}. \ref{fig:tlc7528_pinout}.
A R2R DAC is a dac which can sample very fast with very low internal noise due
to the internal structure and low complexity.\cite{boehmer} These features are
important for audio applications.
\begin{figure}[H] \begin{figure}[H]
\centering \centering

View file

@ -93,3 +93,12 @@ attached. The blue modules below are the level shifters.
\label{fig:fpga_mod} \label{fig:fpga_mod}
\end{figure} \end{figure}
\subsubsection{Further work on the FPGA}
One optional aim was for further examples to be developed for the FPGA which
would interface with the hardware peripherals. These examples were partially
developed and tested, though never recorded due to the currently ongoing
COVID-19 crisis. These examples may be found inside the documentation of the
processor part of this thesis or on the flash drive which comes with this
thesis.

View file

@ -161,3 +161,38 @@ result the DAC and Serial Communication interface were chosen as peripherals.
\caption{utility analysis results for peripherals} \caption{utility analysis results for peripherals}
\label{tab:utility_result} \label{tab:utility_result}
\end{table} \end{table}
\subsubsection{Material and Infrastructure cost}
The peripherals were mostly constructed with materials currently in stock at
the Hackerspace Innsbruck. This limitation, while driving development time up,
reduced the material cost significantly as resistors, capacitors and most
standard logic ICs were in stock for the purpose of such projects. The materials
which had to be ordered and were used in the final implementation of the
peripherals are listed in Table \ref{tab:cost_hw}. Infrastructure usage at the
Hackerspace is unlimted to anyone who is working on a project and a member of
the community and free of charge.
\begin{table}[H]
\centering
\resizebox{\textwidth}{!}{
\begin{tabular}{ |l|c|c|}
\hline
\textbf{Name} & \textbf{Cost} & \textbf{Quantity}\\
\hline
\hline
ADC 8bit RS-COMPONENTS & € 4.16 &3\\
\hline
8-bit D-Latch RS-COMPONENTS & € 2.21 &4\\
\hline
MAX232 RS-COMPONENTS & € 2.19 &2\\
\hline
Quartz, 1,8432 MHz POLLIN & € 0.15 &4\\
\hline
\hline
\end{tabular}
}
\caption{List of ordered components and cost}
\label{tab:cost_hw}
\end{table}