105 lines
3.7 KiB
TeX
105 lines
3.7 KiB
TeX
\subsection{FPGA to Hardware interface}
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To make the Hardware work with the FPGA's 3.3V I/O, level shifter have been
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installed, and a FPGA module was built. This module maps the I/O Pins in a
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similar
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way to the ATMega 2560 used in examples before. The bidirectional 5V<->3.3V
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logic level converters have been obtained on amazon, and are not well
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documented. Their functionality is tested and verified in both directions,
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which can be seen in figures \ref{fig:3v35v} and \ref{fig:5v3v3}. The schematic
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was determined through measurements with a multimeter, and the
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schematic in Figure \ref{fig:schem_lvlshift} shows similar resistor values in
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the same configuration \cite{lvlshift}.
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\begin{figure}[H]
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\begin{tikzpicture}
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\begin{axis}[
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ylabel=Lane Voltage,
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xlabel=Time,
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grid=both,
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xmin=-1.151135531135531e-06,
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xmax=5.488864468864469e-06,
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minor tick num=5,
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width=\textwidth,
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height=0.5\textheight]
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\addplot table [x=t, y=c1, col sep=comma, mark=none] {meas/20200301shift3v35v.csv};
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\addplot table [x=t, y=c2, col sep=comma, mark=none] {meas/20200301shift3v35v.csv};
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\legend{LV-Side,HV-Side}
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\end{axis}
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\end{tikzpicture}
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\caption{3.3V to 5V conversion using the level shifter}
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\label{fig:3v35v}
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\end{figure}
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The in Figure \ref{fig:3v35v} shown output on the HV side corresponds with the
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schematics in Figure \ref{fig:schem_lvlshift}, where one can see, that the
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resistor R2 is loading the bus capacitance to a 5V high state.
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\begin{figure}[H]
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\begin{tikzpicture}
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\begin{axis}[
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ylabel=Lane Voltage,
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xlabel=Time,
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grid=both,
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xmin=-7.427469135802469e-07,
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xmax=3.567253086419753e-06,
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minor tick num=5,
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width=\textwidth,
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height=0.5\textheight]
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\addplot table [x=t, y=c1, col sep=comma, mark=none] {meas/20200301shift5v3v3.csv};
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\addplot table [x=t, y=c2, col sep=comma, mark=none] {meas/20200301shift5v3v3.csv};
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\legend{LV-Side,HV-Side}
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\end{axis}
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\end{tikzpicture}
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\caption{5V to 3.3V conversion using the level shifter}
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\label{fig:5v3v3}
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\end{figure}
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\begin{figure}[H]
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\centering
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\includegraphics[height=.4\textheight, angle=0]{pics/bidirectonal-mosfet-level-shifter.png}
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\caption{The internal schematics of the level shifter\cite{lvlshift}}
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\label{fig:schem_lvlshift}
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\end{figure}
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\subsubsection{Measurement error}
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During an attempt to measure wether the level shifters in the final module were
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working, a measurement between the LV and the HV side showed only a difference
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of 0.7V. After some troubleshooting, it was found, that the Analog Discovery has
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clamping diodes against the 3.3V rail shown in figure \ref{fig:ad2_diode}. These
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diodes produce the 0.7V offset and prevent the parallel bus from rising to
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5V when a digial I/O pin of the Analog Discovery 2 is connected to the bus.
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\cite{DB3S406F0L}.
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\begin{figure}[H]
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\centering
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\includegraphics[height=.4\textheight, angle=0]{pics/ad2_dio.png}
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\caption{The internal clamping diodes of the Analog Discovery 2\cite{ad2}}
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\label{fig:ad2_diode}
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\end{figure}
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\subsubsection{Final Module}
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The final module can be seen in figure \ref{fig:fpga_mod} without the FPGA
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attached. The blue modules below are the level shifters.
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\begin{figure}[H]
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\centering
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\includegraphics[width=\textwidth, angle=0]{pics/fpga_int}
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\caption{The final FPGA interface module with the level shifters}
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\label{fig:fpga_mod}
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\end{figure}
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\subsubsection{Further work on the FPGA}
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One optional aim was for further examples to be developed for the FPGA which
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would interface with the hardware peripherals. These examples were partially
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developed and tested, though never recorded due to the currently ongoing
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COVID-19 crisis. These examples may be found inside the documentation of the
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processor part of this thesis or on the flash drive which comes with this
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thesis.
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