diff --git a/bibliographies/DP.bib b/bibliographies/DP.bib index 07a6a30..af531bf 100644 --- a/bibliographies/DP.bib +++ b/bibliographies/DP.bib @@ -207,6 +207,13 @@ author = {Unknown Author}, url = {https://www.nxp.com/docs/en/user-guide/UM10204.pdf} } +@book{boehmer, + year = {2009}, + month = Aug, + title = {Elemente der angewandten Elektronik}, + publisher = {Viehweg}, + author = {Erwin Böhmer, Dietmar Erhardt, Wolfgang Oberschlep} +} @Manual{ddc, year = {2007}, month = Dec, diff --git a/main.pdf b/main.pdf index b524802..97939cb 100644 --- a/main.pdf +++ b/main.pdf @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9cf253f620c4c4b1800e21b58f30642be9b19bdbdbfa23c790adf81a25c4654d -size 3556721 +oid sha256:8646e4f3067205fc3ee275655dd4d43ec936610d171b3ffa3c20b74b00788918 +size 3636031 diff --git a/main.tex b/main.tex index ac8f20a..ac66418 100644 --- a/main.tex +++ b/main.tex @@ -190,6 +190,7 @@ geschlechtsunabh"angig verstanden werden soll. \allAuth\input{sections/Anhang/Projektterminplanung/projektterminplanung.tex} \allAuth\input{sections/Anhang/flash.tex} +\DP\input{sections/Anhang/qualitaetssicherung.tex} \AB\subfile{sections/vhdl_intro/vhdl_intro.tex} \end{appendices} diff --git a/sections/Anhang/Projektterminplanung/projektterminplanung.tex b/sections/Anhang/Projektterminplanung/projektterminplanung.tex index 7481ea5..8dd7c32 100644 --- a/sections/Anhang/Projektterminplanung/projektterminplanung.tex +++ b/sections/Anhang/Projektterminplanung/projektterminplanung.tex @@ -63,11 +63,11 @@ Table \ref{tab:brauns_work} shows the times worked. \textbf{Date} & \textbf{Duration [h]} & \textbf{Task}\\ \hline \hline - 2018-12-11 & 3 & Create Quartus project, implement first proof-of-concept design \\ + 2018-12-11 & 3 & Cimplement first proof-of-concept design \\ \hline 2018-12-19 & 3 & ALU design and corresponding test bench \\ \hline - 2019-01-18 & 5 & First processor prototype capable of running programs \\ + 2019-01-18 & 5 & First processor prototype \\ \hline 2019-01-20 & 2 & Preliminary firmware build system \\ \hline @@ -109,7 +109,7 @@ Table \ref{tab:brauns_work} shows the times worked. \hline 2019-03-04 & 1 & Misc bug fixes \\ \hline - 2019-03-10 & 2 & Diagnose and fix interrupt related processor bug \\ + 2019-03-10 & 2 & Fix interrupt related processor bug \\ \hline 2019-03-11 & 3 & CSR illegal instruction exceptions \\ \hline @@ -246,7 +246,7 @@ Table \ref{tab:brauns_work} shows the times worked. 2020-03-31 & 4 & Documentation \\ \hline \hline - 2020-04-01 & \textbf{SUM during school year} & 150h\\ + \multicolumn{2}{c}{\textbf{SUM during school year}} & 150h\\ \hline \caption{Work time reference - Brauns} \label{tab:brauns_work} diff --git a/sections/Anhang/flash.tex b/sections/Anhang/flash.tex index d97459f..963ce6c 100644 --- a/sections/Anhang/flash.tex +++ b/sections/Anhang/flash.tex @@ -38,7 +38,7 @@ Plank respectively. \textbf{Directory} & \textbf{Contents}\\ \hline \hline - code & Code sampkes written for this thesis\\ + code & Code samples written for this thesis\\ \hline dipl & The source code for this thesis in \LaTeX\\ \hline diff --git a/sections/Anhang/qualitaetssicherung.tex b/sections/Anhang/qualitaetssicherung.tex new file mode 100644 index 0000000..9f701e7 --- /dev/null +++ b/sections/Anhang/qualitaetssicherung.tex @@ -0,0 +1,32 @@ +\section{Qualitätssicherung nach ISO-9003} + +Im zuge der Qualitätssicherung nach ISO-9003 wurden für die Hardwareperipherie +laufend Messungen zur Funktionsprüfungen durchgeführt sowie für den Prozessor +diverse Simulationsmodelle erstellt und verwendet. Der Messverlauf wurde +beschrieben und die Messungen mit dem Soll-Wert verglichen. Zur Verifikation +der in MS1 gesammelten PDF-Dateien wurde ein Shell-Skript verfasst, welches +in Listing \ref{lst:mst-t1} eingesehen werden kann. Die Tests verifizieren nach +dem Grobdesign welches in der Abgabe zu Meilenstein 1 auf dem dieser +Diplomarbeit beigelegten Datenträger eingesehen werden kann. + +\begin{lstlisting}[language=bash,frame=trBL, + breaklines=true, breakautoindent=true, formfeed=\newpage, + label={lst:mst-t1}, + caption={Shell-Skript zum Testen der PDF-Dokumente}, + columns=flexible] + +#!/bin/bash + +for f in *.pdf; do + echo "########################################" + echo "Tesing $f..." + echo "########################################" >> ./logfile + if pdfinfo "$f" >> ./logfile; then + echo "$f is correct!" + else + echo "$f is broken!" + fi + echo "########################################" +done + +\end{lstlisting} diff --git a/sections/DP/dac/main.tex b/sections/DP/dac/main.tex index bc87376..15df23c 100644 --- a/sections/DP/dac/main.tex +++ b/sections/DP/dac/main.tex @@ -20,6 +20,9 @@ DAC was developed for audio aplications\cite{tlc7528}, which made its use obvious. The TLC-7528 was the only IC available as DIP \footnote{DIP... Dual Inline Package}, of which the pinout can be seen in Figure \ref{fig:tlc7528_pinout}. +A R2R DAC is a dac which can sample very fast with very low internal noise due +to the internal structure and low complexity.\cite{boehmer} These features are +important for audio applications. \begin{figure}[H] \centering diff --git a/sections/DP/fpga_interface/main.tex b/sections/DP/fpga_interface/main.tex index a40cb7c..113d2a2 100644 --- a/sections/DP/fpga_interface/main.tex +++ b/sections/DP/fpga_interface/main.tex @@ -93,3 +93,12 @@ attached. The blue modules below are the level shifters. \label{fig:fpga_mod} \end{figure} +\subsubsection{Further work on the FPGA} + +One optional aim was for further examples to be developed for the FPGA which +would interface with the hardware peripherals. These examples were partially +developed and tested, though never recorded due to the currently ongoing +COVID-19 crisis. These examples may be found inside the documentation of the +processor part of this thesis or on the flash drive which comes with this +thesis. + diff --git a/sections/DP/plan.tex b/sections/DP/plan.tex index 1bcd931..9424510 100644 --- a/sections/DP/plan.tex +++ b/sections/DP/plan.tex @@ -161,3 +161,38 @@ result the DAC and Serial Communication interface were chosen as peripherals. \caption{utility analysis results for peripherals} \label{tab:utility_result} \end{table} +\subsubsection{Material and Infrastructure cost} + +The peripherals were mostly constructed with materials currently in stock at +the Hackerspace Innsbruck. This limitation, while driving development time up, +reduced the material cost significantly as resistors, capacitors and most +standard logic ICs were in stock for the purpose of such projects. The materials +which had to be ordered and were used in the final implementation of the +peripherals are listed in Table \ref{tab:cost_hw}. Infrastructure usage at the +Hackerspace is unlimted to anyone who is working on a project and a member of +the community and free of charge. + +\begin{table}[H] + \centering + \resizebox{\textwidth}{!}{ + \begin{tabular}{ |l|c|c|} + \hline + \textbf{Name} & \textbf{Cost} & \textbf{Quantity}\\ + \hline + \hline + ADC 8bit RS-COMPONENTS & € 4.16 &3\\ + \hline + 8-bit D-Latch RS-COMPONENTS & € 2.21 &4\\ + \hline + MAX232 RS-COMPONENTS & € 2.19 &2\\ + \hline + Quartz, 1,8432 MHz POLLIN & € 0.15 &4\\ + \hline + \hline + + \end{tabular} + } + \caption{List of ordered components and cost} + \label{tab:cost_hw} +\end{table} +