dipl/vhdl_intro/vhdl_intro.tex

\documentclass[../Diplomschrift.tex]{subfiles}
\begin{document}

\part{A short introduction to VHDL}

Designing a processor is a big task, and it's easiest to start very small. With software projects, this is usually in the form of a ``Hello World'' program - we will be designing a hardware equivalent of this.

\section{Prerequisites}

Other than a text editor, the following Free Software packages have to be installed:

\begin{savenotes}
\begin{description}
 \item[\icode{ghdl}\footnote{\url{https://github.com/ghdl/ghdl}}] to analyze, compile, and simulate the design
 \item[\icode{gtkwave}\footnote{\url{http://gtkwave.sourceforge.net/}}] to view the simulation waveform files
 \item[\icode{yosys}\footnote{\url{http://www.clifford.at/yosys/}}] to synthesize the design
 \item[\icode{nextpnr-xilinx}\footnote{\url{https://github.com/daveshah1/nextpnr-xilinx}}] to place and route the design 
 \item[\icode{Project X-Ray}\footnote{\url{https://github.com/SymbiFlow/prjxray}}] for FPGA layout data and bitstream tools
 \item[\icode{xc3sprog}\footnote{\url{https://sourceforge.net/projects/xc3sprog/}}] to load the bitstream onto the FPGA 
\end{description}
\end{savenotes}

\section{Creating a design}

A simple starting design is an up/down counter. The following VHDL code describes the device:

\lstinputlisting[title=\texttt{counter.vhd}]{vhdl/counter.vhd}

In order to test this design, a test bench has to be created:

\lstinputlisting[title=\texttt{counter\_tb.vhd}]{vhdl/counter_tb.vhd}

\section{Simulating a design}

\begin{lstlisting}[style=default,language=sh]
# analyze the design files
ghdl -a --std=08 *.vhd
# elaborate the test bench entity
ghdl -e --std=08 counter_tb
# run the test bench, saving the signal trace to a GHW file
ghdl -r --std=08 counter_tb --wave=counter_tb.ghw
# open the trace with gtkwave (using the view configuration in counter_tb.gtkw)
gtkwave counter_tb.ghw counter_tb.gtkw
\end{lstlisting}

\begin{center}
\includegraphics[width=\textwidth]{counter_gtkwave.png}
\end{center}

\section{Synthesizing a design}

An additional Xilinx Design Constraints (XDC) file is required to assign the signals to pins on the FPGA:

\lstinputlisting[style=default,title=\texttt{counter.xdc}]{vhdl/counter.xdc}

\begin{lstlisting}[style=default,language=sh]
# synthesize with yosys
yosys -m ghdl.so -p '
    ghdl --std=08 counter.vhd -e counter;
    synth_xilinx -flatten;
    write_json counter.json'
# place and route the design with nextpnr
nextpnr-xilinx --chipdb xc7a35tcsg324-1.bin --xdc counter.xdc --json counter.json --fasm counter.fasm
# convert the FPGA assembly to frames
fasm2frames.py --part xc7a35tcsg324-1 counter.fasm counter.frames
# convert the frames to a bitstream
xc7frames2bit --part-name xc7a35tcsg324-1 --frm-file counter.frames --output-file counter.bit
# upload the bitstream to the FPGA
xc3sprog -c nexys4 counter.bit
\end{lstlisting}

The current value of the counter is displayed in binary on the eight LEDs on the board. When switch 0 (enable) is in the high position, the counter can be advanced using button 0, with the direction set by switch 1. Button 1 resets the counter to zero.

\end{document}