74 lines
3.1 KiB
TeX
74 lines
3.1 KiB
TeX
\documentclass[../Diplomschrift.tex]{subfiles}
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\begin{document}
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\part{A short introduction to VHDL}
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Designing a processor is a big task, and it's easiest to start very small. With software projects, this is usually in the form of a ``Hello World'' program - we will be designing a hardware equivalent of this.
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\section{Prerequisites}
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Other than a text editor, the following Free Software packages have to be installed:
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\begin{savenotes}
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\begin{description}
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\item[\icode{ghdl}\footnote{\url{https://github.com/ghdl/ghdl}}] to analyze, compile, and simulate the design
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\item[\icode{gtkwave}\footnote{\url{http://gtkwave.sourceforge.net/}}] to view the simulation waveform files
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\item[\icode{yosys}\footnote{\url{http://www.clifford.at/yosys/}}] to synthesize the design
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\item[\icode{nextpnr-xilinx}\footnote{\url{https://github.com/daveshah1/nextpnr-xilinx}}] to place and route the design
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\item[\icode{Project X-Ray}\footnote{\url{https://github.com/SymbiFlow/prjxray}}] for FPGA layout data and bitstream tools
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\item[\icode{xc3sprog}\footnote{\url{https://sourceforge.net/projects/xc3sprog/}}] to load the bitstream onto the FPGA
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\end{description}
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\end{savenotes}
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\section{Creating a design}
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A simple starting design is an up/down counter. The following VHDL code describes the device:
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\lstinputlisting[title=\texttt{counter.vhd}]{vhdl/counter.vhd}
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In order to test this design, a test bench has to be created:
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\lstinputlisting[title=\texttt{counter\_tb.vhd}]{vhdl/counter_tb.vhd}
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\section{Simulating a design}
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\begin{lstlisting}[style=default,language=sh]
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# analyze the design files
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ghdl -a --std=08 *.vhd
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# elaborate the test bench entity
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ghdl -e --std=08 counter_tb
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# run the test bench, saving the signal trace to a GHW file
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ghdl -r --std=08 counter_tb --wave=counter_tb.ghw
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# open the trace with gtkwave (using the view configuration in counter_tb.gtkw)
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gtkwave counter_tb.ghw counter_tb.gtkw
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\end{lstlisting}
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\begin{center}
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\includegraphics[width=\textwidth]{counter_gtkwave.png}
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\end{center}
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\section{Synthesizing a design}
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An additional Xilinx Design Constraints (XDC) file is required to assign the signals to pins on the FPGA:
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\lstinputlisting[style=default,title=\texttt{counter.xdc}]{vhdl/counter.xdc}
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\begin{lstlisting}[style=default,language=sh]
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# synthesize with yosys
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yosys -m ghdl.so -p '
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ghdl --std=08 counter.vhd -e counter;
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synth_xilinx -flatten;
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write_json counter.json'
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# place and route the design with nextpnr
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nextpnr-xilinx --chipdb xc7a35tcsg324-1.bin --xdc counter.xdc --json counter.json --fasm counter.fasm
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# convert the FPGA assembly to frames
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fasm2frames.py --part xc7a35tcsg324-1 counter.fasm counter.frames
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# convert the frames to a bitstream
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xc7frames2bit --part-name xc7a35tcsg324-1 --frm-file counter.frames --output-file counter.bit
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# upload the bitstream to the FPGA
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xc3sprog -c nexys4 counter.bit
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\end{lstlisting}
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The current value of the counter is displayed in binary on the eight LEDs on the board. When switch 0 (enable) is in the high position, the counter can be advanced using button 0, with the direction set by switch 1. Button 1 resets the counter to zero.
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\end{document}
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