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fix(gen_liteeth): fix configurations

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This commit is contained in:
Xiretza 2022-06-03 22:17:13 +02:00
parent d6687786a7
commit eedf254b15
1 changed files with 4 additions and 5 deletions
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9
gen_liteeth.py
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@ -32,7 +32,7 @@ from liteeth.core import LiteEthUDPIPCore
# IOs ---------------------------------------------------------------------------------------------- # IOs ----------------------------------------------------------------------------------------------
MAC_ADDRESS = 0x00183e02a914 MAC_ADDRESS = 0x00183e02a914
CLK_FREQ = int(125e6) CLK_FREQ = int(100e6)
_io = [ _io = [
# Clk / Rst # Clk / Rst
@ -148,11 +148,10 @@ class PHYCore(SoCMini):
) )
# PHY -------------------------------------------------------------------------------------- # PHY --------------------------------------------------------------------------------------
phy = liteeth_phys.LiteEthPHYRMII phy = liteeth_phys.LiteEthPHYMII
ethphy = phy( ethphy = phy(
refclk_cd=None, clock_pads=platform.request("mii_eth_clocks"),
clock_pads=platform.request("rmii_eth_clocks"), pads=platform.request("mii_eth")
pads=platform.request("rmii_eth")
) )
self.submodules.ethphy = ethphy self.submodules.ethphy = ethphy