From eedf254b152af3d3d7ec8daaa8170aa77c1ac251 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Fri, 3 Jun 2022 22:17:13 +0200 Subject: [PATCH] fix(gen_liteeth): fix configurations --- gen_liteeth.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/gen_liteeth.py b/gen_liteeth.py index f43ee95..c66e617 100755 --- a/gen_liteeth.py +++ b/gen_liteeth.py @@ -32,7 +32,7 @@ from liteeth.core import LiteEthUDPIPCore # IOs ---------------------------------------------------------------------------------------------- MAC_ADDRESS = 0x00183e02a914 -CLK_FREQ = int(125e6) +CLK_FREQ = int(100e6) _io = [ # Clk / Rst @@ -148,11 +148,10 @@ class PHYCore(SoCMini): ) # PHY -------------------------------------------------------------------------------------- - phy = liteeth_phys.LiteEthPHYRMII + phy = liteeth_phys.LiteEthPHYMII ethphy = phy( - refclk_cd=None, - clock_pads=platform.request("rmii_eth_clocks"), - pads=platform.request("rmii_eth") + clock_pads=platform.request("mii_eth_clocks"), + pads=platform.request("mii_eth") ) self.submodules.ethphy = ethphy