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vhdl: disable test UDP sender

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Xiretza 2022-06-05 21:35:50 +02:00
parent 9121ccfdbe
commit 79fce1afc1
1 changed files with 1 additions and 1 deletions
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vhdl/arty_a7.vhdl
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@ -307,7 +307,7 @@ begin
if counter = COUNTER_MAX then if counter = COUNTER_MAX then
pixel_sink_length <= std_logic_vector(to_unsigned(NUM_WORDS, 16)); pixel_sink_length <= std_logic_vector(to_unsigned(NUM_WORDS, 16));
pixel_sink_data <= std_logic_vector(to_unsigned(16#30# + words_sent, 32)); pixel_sink_data <= std_logic_vector(to_unsigned(16#30# + words_sent, 32));
pixel_sink_valid <= '1'; --pixel_sink_valid <= '1';
pixel_sink_last <= '1' when words_sent = NUM_WORDS-1 else '0'; pixel_sink_last <= '1' when words_sent = NUM_WORDS-1 else '0';