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vhdl: rename clk_sys to sys_clk

This commit is contained in:
Xiretza 2022-06-05 16:44:35 +02:00
parent 57e6daedcc
commit 2ec250e79d
2 changed files with 11 additions and 11 deletions
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2
arty_a7_35.xdc
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@ -222,7 +222,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[15]}]
create_clock -period 12.5 [get_nets clk_sys] create_clock -period 12.5 [get_nets sys_clk]
create_clock -period 40.0 [get_nets liteeth_inst.eth_rx_clk] create_clock -period 40.0 [get_nets liteeth_inst.eth_rx_clk]
create_clock -period 40.0 [get_nets liteeth_inst.eth_tx_clk] create_clock -period 40.0 [get_nets liteeth_inst.eth_tx_clk]

20
vhdl/arty_a7.vhdl
View File

@ -168,8 +168,8 @@ architecture a of arty_a7 is
signal pll_feedback : std_logic; signal pll_feedback : std_logic;
signal pll_locked : std_logic; signal pll_locked : std_logic;
signal unbuf_clk_sys : std_logic; signal unbuf_sys_clk : std_logic;
signal clk_sys : std_logic; signal sys_clk : std_logic;
component BUFG component BUFG
port ( port (
@ -192,7 +192,7 @@ begin
ck_dig_h <= (others => 'Z'); ck_dig_h <= (others => 'Z');
liteeth_inst: liteeth_core port map ( liteeth_inst: liteeth_core port map (
sys_clock => clk_sys, sys_clock => sys_clk,
sys_reset => sys_reset, sys_reset => sys_reset,
mii_eth_clocks_tx => mii_tx_clk, mii_eth_clocks_tx => mii_tx_clk,
@ -270,14 +270,14 @@ begin
CLKFBIN => pll_feedback, CLKFBIN => pll_feedback,
CLKFBOUT => pll_feedback, CLKFBOUT => pll_feedback,
CLKOUT0 => unbuf_clk_sys, CLKOUT0 => unbuf_sys_clk,
CLKOUT1 => mii_clk_25mhz CLKOUT1 => mii_clk_25mhz
); );
bufg_clk_sys: BUFG bufg_sys_clk: BUFG
port map ( port map (
I => unbuf_clk_sys, I => unbuf_sys_clk,
O => clk_sys O => sys_clk
); );
sys_reset <= not pll_locked or not n_reset; sys_reset <= not pll_locked or not n_reset;
@ -286,14 +286,14 @@ begin
pmod_b <= drivers(15 downto 8); pmod_b <= drivers(15 downto 8);
pmod_d <= drivers(23 downto 16); pmod_d <= drivers(23 downto 16);
sender: process(clk_sys) sender: process(sys_clk)
constant COUNTER_MAX: natural := 80000000; constant COUNTER_MAX: natural := 80000000;
variable counter: natural range 0 to COUNTER_MAX; variable counter: natural range 0 to COUNTER_MAX;
constant NUM_WORDS: natural := 10; constant NUM_WORDS: natural := 10;
variable words_sent: natural range 0 to NUM_WORDS; variable words_sent: natural range 0 to NUM_WORDS;
begin begin
if rising_edge(clk_sys) then if rising_edge(sys_clk) then
if counter = COUNTER_MAX then if counter = COUNTER_MAX then
pixel_sink_length <= std_logic_vector(to_unsigned(NUM_WORDS, 16)); pixel_sink_length <= std_logic_vector(to_unsigned(NUM_WORDS, 16));
pixel_sink_data <= std_logic_vector(to_unsigned(16#30# + words_sent, 32)); pixel_sink_data <= std_logic_vector(to_unsigned(16#30# + words_sent, 32));
@ -320,7 +320,7 @@ begin
NUM_DRIVERS => NUM_DRIVERS NUM_DRIVERS => NUM_DRIVERS
) )
port map ( port map (
clk => clk_sys, clk => sys_clk,
reset => sys_reset, reset => sys_reset,
drivers => drivers drivers => drivers