From 2ec250e79d0b14bd2010c113842ad3dc262e2215 Mon Sep 17 00:00:00 2001
From: Xiretza <xiretza@xiretza.xyz>
Date: Sun, 5 Jun 2022 16:44:35 +0200
Subject: [PATCH] vhdl: rename clk_sys to sys_clk

---
 arty_a7_35.xdc    |  2 +-
 vhdl/arty_a7.vhdl | 20 ++++++++++----------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arty_a7_35.xdc b/arty_a7_35.xdc
index 5bfa126..1e5ed19 100644
--- a/arty_a7_35.xdc
+++ b/arty_a7_35.xdc
@@ -222,7 +222,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[13]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[14]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[15]}]
 
-create_clock -period 12.5 [get_nets clk_sys]
+create_clock -period 12.5 [get_nets sys_clk]
 
 create_clock -period 40.0 [get_nets liteeth_inst.eth_rx_clk]
 create_clock -period 40.0 [get_nets liteeth_inst.eth_tx_clk]
diff --git a/vhdl/arty_a7.vhdl b/vhdl/arty_a7.vhdl
index e079fa2..b2c547f 100644
--- a/vhdl/arty_a7.vhdl
+++ b/vhdl/arty_a7.vhdl
@@ -168,8 +168,8 @@ architecture a of arty_a7 is
 
 	signal pll_feedback : std_logic;
 	signal pll_locked : std_logic;
-	signal unbuf_clk_sys : std_logic;
-	signal clk_sys : std_logic;
+	signal unbuf_sys_clk : std_logic;
+	signal sys_clk : std_logic;
 
 	component BUFG
 		port (
@@ -192,7 +192,7 @@ begin
 	ck_dig_h <= (others => 'Z');
 
 	liteeth_inst: liteeth_core port map (
-		sys_clock => clk_sys,
+		sys_clock => sys_clk,
 		sys_reset => sys_reset,
 
 		mii_eth_clocks_tx => mii_tx_clk,
@@ -270,14 +270,14 @@ begin
 			CLKFBIN  => pll_feedback,
 			CLKFBOUT => pll_feedback,
 
-			CLKOUT0 => unbuf_clk_sys,
+			CLKOUT0 => unbuf_sys_clk,
 			CLKOUT1 => mii_clk_25mhz
 		);
 
-	bufg_clk_sys: BUFG
+	bufg_sys_clk: BUFG
 		port map (
-			I => unbuf_clk_sys,
-			O => clk_sys
+			I => unbuf_sys_clk,
+			O => sys_clk
 		);
 
 	sys_reset <= not pll_locked or not n_reset;
@@ -286,14 +286,14 @@ begin
 	pmod_b <= drivers(15 downto 8);
 	pmod_d <= drivers(23 downto 16);
 
-	sender: process(clk_sys)
+	sender: process(sys_clk)
 		constant COUNTER_MAX: natural := 80000000;
 		variable counter: natural range 0 to COUNTER_MAX;
 
 		constant NUM_WORDS: natural := 10;
 		variable words_sent: natural range 0 to NUM_WORDS;
 	begin
-		if rising_edge(clk_sys) then
+		if rising_edge(sys_clk) then
 			if counter = COUNTER_MAX then
 				pixel_sink_length <= std_logic_vector(to_unsigned(NUM_WORDS, 16));
 				pixel_sink_data <= std_logic_vector(to_unsigned(16#30# + words_sent, 32));
@@ -320,7 +320,7 @@ begin
 			NUM_DRIVERS => NUM_DRIVERS
 		)
 		port map (
-			clk => clk_sys,
+			clk => sys_clk,
 			reset => sys_reset,
 
 			drivers => drivers