splink/Makefile

.SECONDARY:

SYNTH_TOOLCHAIN ?= nextpnr

WORKDIR            = work
GHDL_WORKDIR       = $(WORKDIR)/ghdl
SYMBIYOSYS_WORKDIR = $(WORKDIR)/symbiyosys
LITEX_WORKDIR      = $(WORKDIR)/litex
SYNTH_WORKDIR      = $(WORKDIR)/synth/$(SYNTH_TOOLCHAIN)

SIM_DIR   = sim
VHDL_DIR  = vhdl

WORKLIB_NAME = splink

VHDL_FILES = $(wildcard $(VHDL_DIR)/*.vhdl $(VHDL_DIR)/ws2812_vhdl/*.vhd)
VERILOG_FILES = $(LITEX_WORKDIR)/gateware/liteeth_core.v
SBY_FILES =

SIM_ENTITY        = splink_tb
SYNTH_ENTITY      = arty_a7
YOSYS_MODULE_NAME = arty_a7

GHDL = ghdl
VHDL_STD = 08
GHDL_FLAGS    = --std=$(VHDL_STD) --work=$(WORKLIB_NAME) --workdir=$(GHDL_WORKDIR) -g
SIM_RUN_FLAGS = --max-stack-alloc=0 --assert-level=warning --ieee-asserts=disable-at-0

GTKWAVE = gtkwave

# synthesis

XDC = arty_a7_35.xdc

PART = xc7a35tcsg324-1

YOSYS = yosys

XRAY_DATABASE = /usr/share/xray/database/artix7

NEXTPNR = nextpnr-xilinx
BBASM   = bbasm
FASM2FRAMES = fasm2frames
FRAMES2BIT  = xc7frames2bit
OPENFPGALOADER = openFPGALoader

GHDL_YOSYS_PLUGIN = ghdl

SBY = sby -fd '$(SYMBIYOSYS_WORKDIR)' --yosys='$(YOSYS) -m $(GHDL_YOSYS_PLUGIN)'

# ====================
# END OF CONFIGURATION
# ====================

.PHONY: default
default: bitstream

SIM_WAVE = $(SIM_DIR)/$(SIM_ENTITY).ghw
# for only capturing select signals
SIM_WAVEOPTS = $(SIM_DIR)/$(SIM_ENTITY).waveopt
SIM_WAVE_SAVE = $(SIM_DIR)/$(SIM_ENTITY).gtkw

ifneq (,$(wildcard $(SIM_WAVEOPTS)))
SIM_RUN_FLAGS += --read-wave-opt=$(SIM_WAVEOPTS)
endif

ifeq ($(SYNTH_TOOLCHAIN),symbiflow)
include Makefile.symbiflow
else ifeq ($(SYNTH_TOOLCHAIN),nextpnr)
include Makefile.nextpnr
else
$(error Bad PNR toolchain: expected one of symbiflow, nextpnr)
endif

$(GHDL_WORKDIR) $(SYNTH_WORKDIR):
	mkdir -p $@

$(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf: | $(GHDL_WORKDIR)
	$(GHDL) import $(GHDL_FLAGS) $(VHDL_FILES)

$(LITEX_WORKDIR)/gateware/liteeth_core.v: gen_liteeth.py
	./gen_liteeth.py --output-dir $(LITEX_WORKDIR)

# =======
# PHONIES
# =======

.PHONY: simonly
simonly: $(VHDL_FILES) | $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf
	$(GHDL) make $(GHDL_FLAGS) $(SIM_ENTITY)
	$(GHDL) run $(GHDL_FLAGS) $(SIM_ENTITY) $(SIM_RUN_FLAGS)

.PHONY: wave
wave: $(VHDL_FILES)
	$(GHDL) make $(GHDL_FLAGS) $(SIM_ENTITY)
	$(GHDL) run $(GHDL_FLAGS) $(SIM_ENTITY) $(SIM_RUN_FLAGS) --wave=$(SIM_WAVE)
	$(GTKWAVE) $(SIM_WAVE) $(SIM_WAVE_SAVE)

.PHONY: check
check: check-formal

.PHONY: check-formal
check-formal:
	$(foreach f,$(SBY_FILES),$(SBY) $(f))

.PHONY: synth
synth: $(SYNTH_OUTPUT_FILE)

.PHONY: show
show: $(SYNTH_OUTPUT_FILE)
	$(YOSYS) -p show $<

.PHONY: bitstream
bitstream: $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).bit

.PHONY: flash
flash: $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).bit
	$(OPENFPGALOADER) -b arty $<

.PHONY: clean
clean:
	rm -rf $(WORKDIR)