123 lines
2.7 KiB
Makefile
123 lines
2.7 KiB
Makefile
.SECONDARY:
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SYNTH_TOOLCHAIN ?= nextpnr
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WORKDIR = work
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GHDL_WORKDIR = $(WORKDIR)/ghdl
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SYMBIYOSYS_WORKDIR = $(WORKDIR)/symbiyosys
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LITEX_WORKDIR = $(WORKDIR)/litex
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SYNTH_WORKDIR = $(WORKDIR)/synth/$(SYNTH_TOOLCHAIN)
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SIM_DIR = sim
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VHDL_DIR = vhdl
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WORKLIB_NAME = splink
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VHDL_FILES = $(wildcard $(VHDL_DIR)/*.vhdl $(VHDL_DIR)/ws2812_vhdl/*.vhd)
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VERILOG_FILES = $(LITEX_WORKDIR)/gateware/liteeth_core.v
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SBY_FILES =
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SIM_ENTITY = splink_tb
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SYNTH_ENTITY = arty_a7
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YOSYS_MODULE_NAME = arty_a7
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GHDL = ghdl
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VHDL_STD = 08
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GHDL_FLAGS = --std=$(VHDL_STD) --work=$(WORKLIB_NAME) --workdir=$(GHDL_WORKDIR) -g
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SIM_RUN_FLAGS = --max-stack-alloc=0 --assert-level=warning --ieee-asserts=disable-at-0
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GTKWAVE = gtkwave
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# synthesis
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XDC = arty_a7_35.xdc
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PART = xc7a35tcsg324-1
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YOSYS = yosys
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XRAY_DATABASE = /usr/share/xray/database/artix7
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NEXTPNR = nextpnr-xilinx
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BBASM = bbasm
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FASM2FRAMES = fasm2frames
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FRAMES2BIT = xc7frames2bit
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OPENFPGALOADER = openFPGALoader
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GHDL_YOSYS_PLUGIN = ghdl
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SBY = sby -fd '$(SYMBIYOSYS_WORKDIR)' --yosys='$(YOSYS) -m $(GHDL_YOSYS_PLUGIN)'
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# ====================
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# END OF CONFIGURATION
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# ====================
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.PHONY: default
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default: bitstream
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SIM_WAVE = $(SIM_DIR)/$(SIM_ENTITY).ghw
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# for only capturing select signals
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SIM_WAVEOPTS = $(SIM_DIR)/$(SIM_ENTITY).waveopt
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SIM_WAVE_SAVE = $(SIM_DIR)/$(SIM_ENTITY).gtkw
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ifneq (,$(wildcard $(SIM_WAVEOPTS)))
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SIM_RUN_FLAGS += --read-wave-opt=$(SIM_WAVEOPTS)
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endif
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ifeq ($(SYNTH_TOOLCHAIN),symbiflow)
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include Makefile.symbiflow
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else ifeq ($(SYNTH_TOOLCHAIN),nextpnr)
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include Makefile.nextpnr
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else
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$(error Bad PNR toolchain: expected one of symbiflow, nextpnr)
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endif
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$(GHDL_WORKDIR) $(SYNTH_WORKDIR):
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mkdir -p $@
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$(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf: | $(GHDL_WORKDIR)
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$(GHDL) import $(GHDL_FLAGS) $(VHDL_FILES)
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$(LITEX_WORKDIR)/gateware/liteeth_core.v: gen_liteeth.py
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./gen_liteeth.py --output-dir $(LITEX_WORKDIR)
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# =======
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# PHONIES
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# =======
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.PHONY: simonly
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simonly: $(VHDL_FILES) | $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf
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$(GHDL) make $(GHDL_FLAGS) $(SIM_ENTITY)
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$(GHDL) run $(GHDL_FLAGS) $(SIM_ENTITY) $(SIM_RUN_FLAGS)
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.PHONY: wave
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wave: $(VHDL_FILES)
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$(GHDL) make $(GHDL_FLAGS) $(SIM_ENTITY)
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$(GHDL) run $(GHDL_FLAGS) $(SIM_ENTITY) $(SIM_RUN_FLAGS) --wave=$(SIM_WAVE)
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$(GTKWAVE) $(SIM_WAVE) $(SIM_WAVE_SAVE)
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.PHONY: check
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check: check-formal
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.PHONY: check-formal
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check-formal:
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$(foreach f,$(SBY_FILES),$(SBY) $(f))
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.PHONY: synth
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synth: $(SYNTH_OUTPUT_FILE)
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.PHONY: show
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show: $(SYNTH_OUTPUT_FILE)
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$(YOSYS) -p show $<
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.PHONY: bitstream
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bitstream: $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).bit
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.PHONY: flash
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flash: $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).bit
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$(OPENFPGALOADER) -b arty $<
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.PHONY: clean
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clean:
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rm -rf $(WORKDIR)
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