day2/vhdl: don't simulate synthesized design by default

This commit is contained in:
Xiretza 2020-12-06 12:12:15 +01:00
parent 26dc74cb53
commit cf81fd7593
Signed by: xiretza
GPG key ID: 17B78226F7139993

View file

@ -3,20 +3,21 @@
set -eu set -eu
INPUT=$1 INPUT=$1
MODE=${2:-}
GHDLFLAGS="--std=08 --workdir=workdir" GHDLFLAGS="--std=08 --workdir=workdir"
mkdir -p workdir mkdir -p workdir
ghdl remove $GHDLFLAGS if [[ $MODE = "--synth" ]]; then
ghdl analyze $GHDLFLAGS parser.vhd verifier.vhd top.vhd sim.vhd for step in 1 2; do
ghdl elab-run $GHDLFLAGS sim -gSTEP=1 < "$INPUT"
ghdl elab-run $GHDLFLAGS sim -gSTEP=2 < "$INPUT"
echo "Synthesized: "
for step in 1 2; do
ghdl remove $GHDLFLAGS ghdl remove $GHDLFLAGS
ghdl synth $GHDLFLAGS -gCOUNTER_WIDTH=12 -gSTEP="$step" parser.vhd verifier.vhd top.vhd -e top > top_syn.vhd ghdl synth $GHDLFLAGS -gCOUNTER_WIDTH=12 -gSTEP="$step" parser.vhd verifier.vhd top.vhd -e top > top_syn.vhd 2>/dev/null
ghdl analyze $GHDLFLAGS top_syn.vhd sim.vhd ghdl analyze $GHDLFLAGS top_syn.vhd sim.vhd
ghdl elab-run $GHDLFLAGS sim -gSTEP="$step" --ieee-asserts=disable < "$INPUT" ghdl elab-run $GHDLFLAGS sim -gSTEP="$step" --ieee-asserts=disable < "$INPUT"
done done
else
ghdl remove $GHDLFLAGS
ghdl analyze $GHDLFLAGS parser.vhd verifier.vhd top.vhd sim.vhd
ghdl elab-run $GHDLFLAGS sim -gSTEP=1 < "$INPUT"
ghdl elab-run $GHDLFLAGS sim -gSTEP=2 < "$INPUT"
fi