From cf81fd759385e20f2037d0c0d9b0611178761e32 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Sun, 6 Dec 2020 12:12:15 +0100 Subject: [PATCH] day2/vhdl: don't simulate synthesized design by default --- day2/vhdl/run.sh | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/day2/vhdl/run.sh b/day2/vhdl/run.sh index 530ec7d..2094a93 100755 --- a/day2/vhdl/run.sh +++ b/day2/vhdl/run.sh @@ -3,20 +3,21 @@ set -eu INPUT=$1 +MODE=${2:-} GHDLFLAGS="--std=08 --workdir=workdir" mkdir -p workdir -ghdl remove $GHDLFLAGS -ghdl analyze $GHDLFLAGS parser.vhd verifier.vhd top.vhd sim.vhd -ghdl elab-run $GHDLFLAGS sim -gSTEP=1 < "$INPUT" -ghdl elab-run $GHDLFLAGS sim -gSTEP=2 < "$INPUT" - -echo "Synthesized: " - -for step in 1 2; do +if [[ $MODE = "--synth" ]]; then + for step in 1 2; do + ghdl remove $GHDLFLAGS + ghdl synth $GHDLFLAGS -gCOUNTER_WIDTH=12 -gSTEP="$step" parser.vhd verifier.vhd top.vhd -e top > top_syn.vhd 2>/dev/null + ghdl analyze $GHDLFLAGS top_syn.vhd sim.vhd + ghdl elab-run $GHDLFLAGS sim -gSTEP="$step" --ieee-asserts=disable < "$INPUT" + done +else ghdl remove $GHDLFLAGS - ghdl synth $GHDLFLAGS -gCOUNTER_WIDTH=12 -gSTEP="$step" parser.vhd verifier.vhd top.vhd -e top > top_syn.vhd - ghdl analyze $GHDLFLAGS top_syn.vhd sim.vhd - ghdl elab-run $GHDLFLAGS sim -gSTEP="$step" --ieee-asserts=disable < "$INPUT" -done + ghdl analyze $GHDLFLAGS parser.vhd verifier.vhd top.vhd sim.vhd + ghdl elab-run $GHDLFLAGS sim -gSTEP=1 < "$INPUT" + ghdl elab-run $GHDLFLAGS sim -gSTEP=2 < "$INPUT" +fi