Xiretza 3ab9f6bb2e 2020 day2/vhdl: don't simulate synthesized design by default		2021-12-01 08:54:50 +01:00
..
.gitignore	2020 day2/vhdl: update gitignore	2021-12-01 08:54:50 +01:00
parser.vhd	2020 day2/vhdl: workaround ghdl#1529	2021-12-01 08:54:50 +01:00
run.sh	2020 day2/vhdl: don't simulate synthesized design by default	2021-12-01 08:54:50 +01:00
sim.gtkw	2020 day2/VHDL: add solution	2021-12-01 08:54:50 +01:00
sim.vhd	read problem inputs from stdin	2021-12-01 08:54:50 +01:00
top.vhd	2020 day2/VHDL: add solution	2021-12-01 08:54:50 +01:00
verifier.vhd	2020 day2/VHDL: add solution	2021-12-01 08:54:50 +01:00