2020 day2/VHDL: add solution
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4
2020/day2/vhdl/.gitignore
vendored
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4
2020/day2/vhdl/.gitignore
vendored
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workdir/
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*.o
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*.ghw
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sim
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86
2020/day2/vhdl/parser.vhd
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86
2020/day2/vhdl/parser.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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entity parser is
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port (
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clk : in std_logic;
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reset : in std_logic;
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is_record : in std_logic;
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is_data : out std_logic;
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char : in character;
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num1, num2 : out natural range 0 to 99;
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letter : out character
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);
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end entity;
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architecture behaviour of parser is
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type state_t is (S_NUM1, S_NUM2, S_LETTER, S_COLON, S_END_SPACE, S_DATA);
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signal state : state_t := S_NUM1;
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subtype digit is natural range 0 to 9;
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type multiples_lookup_t is array(digit) of natural range 0 to 90;
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constant TEN_MULTIPLES : multiples_lookup_t := (0, 10, 20, 30, 40, 50, 60, 70, 80, 90);
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-- most significant digit of number
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signal prev_digit : digit := 0;
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signal current_digit : digit;
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signal complete_num : natural range 0 to 99;
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function char_to_digit(input : in character) return digit is
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begin
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if input >= '0' and input <= '9' then
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return character'pos(input) - character'pos('0');
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else
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return 0;
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end if;
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end function;
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begin
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current_digit <= char_to_digit(char);
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complete_num <= TEN_MULTIPLES(prev_digit) + current_digit;
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process(clk)
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begin
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if rising_edge(clk) then
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if reset then
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prev_digit <= 0;
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state <= S_NUM1;
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else
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prev_digit <= 0;
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case state is
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when S_NUM1 =>
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if is_record then
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if char = '-' then
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state <= S_NUM2;
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else
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num1 <= complete_num;
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prev_digit <= current_digit;
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end if;
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end if;
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when S_NUM2 =>
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if char = ' ' then
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state <= S_LETTER;
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else
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num2 <= complete_num;
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prev_digit <= current_digit;
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end if;
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when S_LETTER =>
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letter <= char;
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state <= S_COLON;
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when S_COLON =>
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state <= S_END_SPACE;
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when S_END_SPACE =>
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state <= S_DATA;
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when S_DATA =>
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if not is_record then
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state <= S_NUM1;
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end if;
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end case;
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end if;
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end if;
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end process;
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is_data <= '1' when state = S_DATA else '0';
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end architecture;
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9
2020/day2/vhdl/run.sh
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2020/day2/vhdl/run.sh
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#!/usr/bin/env sh
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set -eu
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mkdir -p workdir
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ghdl analyze --std=08 --workdir=workdir parser.vhd verifier.vhd top.vhd sim.vhd
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ghdl elab-run --std=08 --workdir=workdir sim -gSTEP=1 -gFILENAME="../input.txt"
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ghdl elab-run --std=08 --workdir=workdir sim -gSTEP=2 -gFILENAME="../input.txt"
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47
2020/day2/vhdl/sim.gtkw
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47
2020/day2/vhdl/sim.gtkw
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Wed Dec 2 10:02:23 2020
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[*]
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[dumpfile] "/home/xiretza/dev/aoc2020/day2/sim.ghw"
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[dumpfile_mtime] "Wed Dec 2 10:01:08 2020"
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[dumpfile_size] 410436
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[savefile] "/home/xiretza/dev/aoc2020/day2/sim.gtkw"
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[timestart] 410945000000
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[size] 1600 853
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[pos] -1 -1
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*-27.864407 226600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] top.
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[treeopen] top.sim.
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[treeopen] top.sim.top.
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[sst_width] 221
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[signals_width] 260
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[sst_expanded] 1
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[sst_vpaned_height] 233
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@28
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top.sim.clk
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top.sim.reset
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top.sim.top.parser_inst.is_record
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@420
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top.sim.top.char
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@200
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-
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@28
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top.sim.top.parser_inst.is_data
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@420
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top.sim.top.num1
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top.sim.top.num2
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top.sim.top.letter
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@200
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-
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@420
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top.sim.top.verifier_inst.count
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@28
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top.sim.top.verifier_inst.verified
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@200
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-
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@24
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#{top.sim.num_verified[11:0]} top.sim.num_verified[11] top.sim.num_verified[10] top.sim.num_verified[9] top.sim.num_verified[8] top.sim.num_verified[7] top.sim.num_verified[6] top.sim.num_verified[5] top.sim.num_verified[4] top.sim.num_verified[3] top.sim.num_verified[2] top.sim.num_verified[1] top.sim.num_verified[0]
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@29
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top.sim.top.record_ended
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[pattern_trace] 1
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[pattern_trace] 0
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88
2020/day2/vhdl/sim.vhd
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2020/day2/vhdl/sim.vhd
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library ieee;
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use ieee.std_logic_1164.all,
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ieee.numeric_std.all;
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use std.textio.all;
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entity sim is
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generic (
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FILENAME : string := "input.txt";
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COUNTER_WIDTH : positive := 12;
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STEP : natural range 1 to 2
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);
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end entity;
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architecture a of sim is
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file file_handle : text open read_mode is FILENAME;
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signal char_in : character;
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signal clk, reset, is_record : std_logic;
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signal num_verified : unsigned(COUNTER_WIDTH-1 downto 0);
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procedure print(s: string) is
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variable l : line;
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begin
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write(l, s);
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writeline(output, l);
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end procedure;
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begin
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process
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variable current_line : line;
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variable current_char : character;
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variable good : boolean;
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procedure cycle_clock is
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begin
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wait for 10 ns;
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clk <= '0';
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wait for 10 ns;
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clk <= '1';
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wait for 0 ns;
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end procedure;
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begin
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clk <= '0';
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is_record <= '0';
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char_in <= NUL;
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reset <= '1';
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cycle_clock;
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reset <= '0';
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cycle_clock;
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lines_loop: loop
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exit lines_loop when endfile(file_handle);
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readline(file_handle, current_line);
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is_record <= '1';
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chars_loop: loop
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read(current_line, current_char, good);
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exit chars_loop when not good;
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char_in <= current_char;
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cycle_clock;
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end loop;
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is_record <= '0';
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cycle_clock;
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end loop;
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cycle_clock;
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print(to_string(to_integer(num_verified)));
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wait;
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end process;
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top: entity work.top
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generic map (
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COUNTER_WIDTH => COUNTER_WIDTH,
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STEP => STEP
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)
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port map (
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clk => clk,
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reset => reset,
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char => char_in,
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is_record => is_record,
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num_verified => num_verified
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);
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end architecture;
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84
2020/day2/vhdl/top.vhd
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2020/day2/vhdl/top.vhd
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library ieee;
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use ieee.std_logic_1164.all,
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ieee.numeric_std.all;
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entity top is
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generic (
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COUNTER_WIDTH : positive;
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STEP : natural range 1 to 2
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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char : in character;
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is_record : in std_logic;
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num_verified : out unsigned(COUNTER_WIDTH-1 downto 0)
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);
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end entity;
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architecture behaviour of top is
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signal is_data : std_logic;
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signal num1, num2 : natural range 0 to 99;
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signal letter : character;
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signal prev_is_record : std_logic;
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signal record_ended : std_logic;
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signal verified : std_logic;
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begin
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record_ended <= prev_is_record and not is_record;
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parser_inst: entity work.parser
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port map (
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clk => clk,
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reset => reset,
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is_record => is_record,
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is_data => is_data,
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char => char,
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num1 => num1,
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num2 => num2,
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letter => letter
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);
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generate_verifier: if step = 1 generate
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verifier_inst: entity work.verifier(step1)
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port map (
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clk => clk,
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reset => reset or record_ended,
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is_data => is_data,
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num1 => num1,
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num2 => num2,
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letter => letter,
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char => char,
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verified => verified
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);
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elsif step = 2 generate
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verifier_inst: entity work.verifier(step2)
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port map (
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clk => clk,
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reset => reset or record_ended,
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is_data => is_data,
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num1 => num1,
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num2 => num2,
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letter => letter,
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char => char,
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verified => verified
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);
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else generate
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assert false report "Bad value for ""step""" severity failure;
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end generate;
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process(clk)
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begin
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if rising_edge(clk) then
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prev_is_record <= is_record;
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if reset then
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prev_is_record <= '0';
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num_verified <= (others => '0');
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elsif record_ended and verified then
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num_verified <= num_verified + 1;
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end if;
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end if;
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end process;
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end architecture;
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58
2020/day2/vhdl/verifier.vhd
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58
2020/day2/vhdl/verifier.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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entity verifier is
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port (
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clk : in std_logic;
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reset : in std_logic;
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is_data : in std_logic;
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num1, num2 : in natural range 0 to 99;
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letter : in character;
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char : in character;
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verified : out std_logic
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);
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end entity;
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architecture step1 of verifier is
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signal count : natural range 0 to 99;
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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if reset then
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count <= 0;
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elsif is_data then
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if char = letter then
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count <= count + 1;
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end if;
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end if;
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end if;
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end process;
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verified <= '1' when num1 <= count and count <= num2 else '0';
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end architecture;
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architecture step2 of verifier is
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signal count : natural range 1 to 99;
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signal parity : std_logic;
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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if reset then
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count <= 1;
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parity <= '0';
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elsif is_data then
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count <= count + 1;
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if (count = num1 or count = num2) and char = letter then
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parity <= not parity;
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end if;
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end if;
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end if;
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end process;
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verified <= parity;
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end architecture;
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