Xiretza 3ab9f6bb2e 2020 day2/vhdl: don't simulate synthesized design by default		2021-12-01 08:54:50 +01:00
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vhdl	2020 day2/vhdl: don't simulate synthesized design by default	2021-12-01 08:54:50 +01:00
day2.py	read problem inputs from stdin	2021-12-01 08:54:50 +01:00