entity registers is
	port (
		clk   : in std_logic;

		read_enable  : in std_logic;
		write_enable : in std_logic;

		addr_a : in register_addr_t;
		addr_b : in register_addr_t;
		addr_d : in register_addr_t;

		data_a : out yarm_word;
		data_b : out yarm_word;
		data_d : in yarm_word
	);
end registers;