dipl/sections/core/entities/decoder_entity.vhd

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484 B
VHDL
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2020-03-27 12:51:39 +01:00
entity decoder is
port (
clk : in std_logic;
enable : in std_logic;
async_addr_rs1 : out register_addr_t;
async_addr_rs2 : out register_addr_t;
alu_muxsel_a : out mux_selector_t;
alu_muxsel_b : out mux_selector_t;
alu_muxsel_cmp2 : out mux_selector_t;
csr_muxsel_in : out mux_selector_t;
instr_info_in : in instruction_info_t;
instr_info_out : out instruction_info_t;
raise_exc : out std_logic;
exc_data : out exception_data_t
);
end decoder;