dipl/sections/core/entities/csr_entity.vhd

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VHDL
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2020-03-27 12:51:39 +01:00
entity csr is
generic (
HART_ID : integer
);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
ready : out std_logic;
instr_info_in : in instruction_info_t;
data_write : in yarm_word;
data_read : out yarm_word;
increase_instret : in std_logic;
external_int : in std_logic;
timer_int : in std_logic;
software_int : in std_logic;
interrupts_pending : out yarm_word;
interrupts_enabled : out yarm_word;
global_int_enabled : out std_logic;
mtvec_out : out yarm_word;
mepc_out : out yarm_word;
do_trap : in std_logic;
return_m_trap : in std_logic;
mepc_in : in yarm_word;
mcause_in : in yarm_trap_cause;
mtval_in : in yarm_word;
raise_exc : out std_logic;
exc_data : out exception_data_t
);
end csr;