Small fixes

Diplomschrift.bib

@@ -60,6 +60,12 @@
     url    = {https://github.com/enjoy-digital/liteeth}
 }
 
+@software{litedram,
+    author = {Florent Kermarrec},
+    title  = {LiteDRAM},
+    url    = {https://github.com/enjoy-digital/litedram}
+}
+
 @software{open-fpga-loader,
 	author = {Gwenhael Goavec-Merou},
 	title  = {openFPGALoader},

preamble.tex

@@ -338,3 +338,5 @@ minimum height=1cm, align=center, text width=3cm, draw=black, fill=blue!30]
 	bottom=0pt
 }
 \newcommand{\icode}[1]{\codeBox{\texttt{#1}}}
+
+\usepackage{booktabs}

sections/soc/soc.tex

@@ -5,7 +5,7 @@
 \part{Meta}
 \section{History}
 
-The project started out with the desire to build a CPU from scratch. Examples such as The NAND Game\cite{nandgame} and Ben Eater's Breadboard Computer series\cite{breadboard_computer} served as inspirations and guidance during development.
+The project started out with the desire to build a CPU from scratch. Examples such as The NAND Game~\cite{nandgame} and Ben Eater's Breadboard Computer series~\cite{breadboard_computer} served as inspirations and guidance during development.
 
 At first, a design similar to Ben Eater's consisting solely of discrete integrated circuits was considered, but soon discarded in favor of an FPGA-based design. Designing the logic alone was a difficult task, implementing it in discrete hardware would have pushed the project far over the allotted maximum development time.
 
@@ -15,28 +15,42 @@ As a starting point, a Terasic DE0 development board\footnote{\url{https://www.t
 
 The only method of synthesis for Altera devices is to use the proprietary Quartus IDE. However, the last version of Quartus to support the Cyclone III series of FPGAs (version 13.1) had already been out of date for several years at the start of the project. Because of this and the increasing resource demand of the developing core, an Arty A7-35T development board\footnote{\url{https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/}} with a Xilinx Artix-7\footnote{\url{https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html}} FPGA was ordered from Digilent.
 
-The two FPGAs compare as follows:
+A comparison between the two FPGAs themselves can be seen in \autoref{tab:fpga-comparison}, a comparison between the peripherals on the development boards in \autoref{tab:devboard-comparison}.
 
-\begin{tabular}{l r r}
+\begin{table}[h]
+\centering
+\begin{tabular}{l|r|r}
+\toprule
                & Altera EP3C16 & Xilinx XC7A35T \\
+\midrule
 Logic Elements & 15000 & 33280 \\
 Multipliers    &    56 &    90 \\
 Block RAM (kb) &   504 &  1800 \\
 PLLs           &     4 &     5 \\
 Global clocks  &    20 &    32 \\
+\bottomrule
 \end{tabular}
+\caption{Comparison between Altera and Xilinx FPGAs}
+\label{tab:fpga-comparison}
+\end{table}
 
-The periphery on the development boards:
-
+\begin{table}[h]
+\centering
 \begin{tabular}{l|r|r}
+\toprule
          & Terasic DE0 & Digilent Arty A7-35T \\
+\midrule
 Switches &           10 & 4 \\
 Buttons  &            3 & 4 \\
 LEDs     & 10 + 4x 7-segment & 4 + 3 RGB \\
 GPIOs    &        2x 36 & 4x PMOD + chipKIT \\
 Memory   &    8MB SDRAM & 256MB DDR3L \\
 Others   & SD card, VGA & Ethernet \\
+\bottomrule
 \end{tabular}
+\caption{Comparison between the peripherals on Terasic and Digilent FPGA development boards}
+\label{tab:devboard-comparison}
+\end{table}
 
 While the Digilent board offers fewer IO options, the DDR3 memory can be interfaced using Free memory cores and allows for much larger programs to be loaded, possibly even a full operating system. The missing VGA port has been substituted by a HDMI-compatible DVI interface that is accessible through one of the high-speed PMOD connectors.
 
@@ -52,16 +66,16 @@ Vendor tools are usually free-of-charge for basic usage, but this also means the
 
 \subsection{Free Software Tools}
 
-A somewhat recent development is the creation of Free Software\footnotemark{} FPGA toolchains. A breakthrough was achieved by Claire (formerly Clifford) Wolf in 2013 with yosys\cite{yosys-paper, yosys}, a feature-complete Verilog synthesis suite for Lattice's \texttt{iCE40} FPGA series.
+A somewhat recent development is the creation of Free Software\footnotemark{} FPGA toolchains. A breakthrough was achieved by Claire (formerly Clifford) Wolf in 2013 with yosys~\cite{yosys-paper, yosys}, a feature-complete Verilog synthesis suite for Lattice's \texttt{iCE40} FPGA series.
     \footnotetext{``Free Software'' refers to software that grants its user the freedom to share, study and modify it - see \url{https://www.fsf.org/about/what-is-free-software}.}
-Since then, both yosys and place-and-route tools like nextpnr\cite{nextpnr} have matured, however Lattice's iCE40 and ECP5 remained the only supported FPGA architectures for place-and-route.
+Since then, both yosys and place-and-route tools like nextpnr~\cite{nextpnr} have matured, however Lattice's iCE40 and ECP5 remained the only supported FPGA architectures for place-and-route.
 
-Thus, two obstacles remained for Free toolchains to be viable for this project: synthesizing \emph{from} VHDL code and synthesizing \emph{to} Artix-7 FPGAs. During the development of the project, both of these were solved: Tristan Gingold released ghdlsynth-beta\parencite*{ghdlsynth-beta}, a bridge between GHDL\cite{ghdl} and yosys allowing VHDL to be synthesized just the same as Verilog, and Dave Shah added Xilinx support to nextpnr\cite{nextpnr-xilinx}. The latter was preceded by many months of volunteer work reverse-engineering the Xilinx bitstream format as part of \textit{Project X-Ray}\parencite*{prjxray}.
+Thus, two obstacles remained for Free toolchains to be viable for this project: synthesizing \emph{from} VHDL code and synthesizing \emph{to} Artix-7 FPGAs. During the development of the project, both of these were solved: Tristan Gingold released ghdlsynth-beta~\cite{ghdlsynth-beta}, a bridge between GHDL~\cite{ghdl} and yosys allowing VHDL to be synthesized just the same as Verilog, and Dave Shah added Xilinx support to nextpnr~\cite{nextpnr-xilinx}. The latter was preceded by many months of volunteer work reverse-engineering the Xilinx bitstream format as part of \textit{Project X-Ray}~\cite{prjxray}.
 
 With these two pieces in place, the project was switched over to a completely Free toolchain, removing any depencies on vendor tools:
 
 \begin{itemize}
- \item yosys, with ghdl as a frontend for processing VHDL, is used to synthesize the design
+ \item yosys, with ghdl as a frontend for processing VHDL and ghdlsynth as a bridge between them, is used to synthesize the design
  \item nextpnr-xilinx, together with the Project X-Ray database, is used for place-and-route
  \item tools from Project X-Ray are used to convert the routed design to a bitstream
  \item openFPGALoader is used to transfer the bitstream to the FPGA via JTAG
@@ -114,7 +128,7 @@ DVI and HDMI are serial digital transmission standards. Three data lines (corres
 
 \subsection{Ethernet}
 
-The Arty development board contains an RJ-45 Ethernet jack connected to an Ethernet PHY, which exposes a standardized media-independent interface (MII) to the FPGA. The LiteEth core\cite{liteeth}, which is released under a Free Software license, is used to integrate the Ethernet interface into the SoC.
+The Arty development board contains an RJ-45 Ethernet jack connected to an Ethernet PHY, which exposes a standardized media-independent interface (MII) to the FPGA. The LiteEth core~\cite{liteeth}, which is released under a Free Software license, is used to integrate the Ethernet interface into the SoC.
 
 \subsection{WS2812 driver}
 
@@ -135,13 +149,15 @@ The driver is designed to be attached to external circuitry that provides color
 
 The LEDs are controlled using a simple one-wire serial protocol. After a reset (long period of logic 0), the data for all LEDs is transmitted serially in one single blob. Each LED consumes and stores the first 24 bits of the stream and applies them as its color value (8 bits each for red, green, blue), all following bits are passed through unmodified. The second LED thus uses the first 24 bits of the stream it receives, but since the first LED already dropped its data, these are actually the second set of 24 bits of the source data.
 
-Every bit is encoded as a period of logic 1, followed by a period of logic 0. The timing of these sections determines the value, see \ref{fig:ws2812_timing}.
+Every bit is encoded as a period of logic 1, followed by a period of logic 0. The timing of these sections determines the value, see \autoref{fig:ws2812_timing}.
 
 The exact timing differs between models, so all periods can be customized using generics in the VHDL entity.
 
 \subsection{DRAM}
 
-% TODO
+The Arty A7 development board contains a 256MB DDR3 memory module. Since the FPGA only contains about 1.8MB of block RAM, of which some is already reserved for various hardware functions (e.g. the text buffer and WS2812 driver), the external memory is absolutely necessary to run larger programs.
+
+Interfacing with DDR3 memory is notoriously difficult, requiring complex logic on both physical and logical layers. For this reason, the Free Software LiteDRAM core~\cite{litedram} is used to integrate the entire memory interface into the SoC. While irrelevant to the SoC, it can still be considered a slight oddity the LiteDRAM core actually contains an entire separate RISC-V core to coordinate initialization of the memory.
 
 \subsection{External Bus}
 
@@ -153,7 +169,7 @@ Due to a mistake in the adapter board layout, the nibbles of the address and dat
 
 \subsection{RISC-V Compliance Tests}
 
-The RISC-V Compliance Test Suite\cite{riscv-compliance} can be used to empirically confirm the correct functionality of a RISC-V processor. It consists of a series of programs that perform some operations related to a specific feature, then write some result data to a memory region. This memory region is then compared to a ``golden signature'', which was produced by a processor implementation that is known to be correct.
+The RISC-V Compliance Test Suite~\cite{riscv-compliance} can be used to empirically confirm the correct functionality of a RISC-V processor. It consists of a series of programs that perform some operations related to a specific feature, then write some result data to a memory region. This memory region is then compared to a ``golden signature'', which was produced by a processor implementation that is known to be correct.
 
 The initial implementation of the compliance tests uncovered several bugs in the processor core:
 

sections/vhdl_intro/vhdl_intro.tex

@@ -59,7 +59,7 @@ gtkwave counter_tb.ghw counter_tb.gtkw
 
 \begin{figure}
 \includegraphics[width=\textwidth]{counter_gtkwave.png}
-\caption{Screenshot of the resulting waveform in GTKWave}
+\caption{Screenshot of the counter test bench waveform in GTKWave}
 \end{figure}
 
 \section{Synthesizing a design}