FINAL COMMIT
This commit concludes the development phase of this thesis as the deadline set in 10 hours from now comes closer and closer and I want to sleep at one point as well. Probably not gonna be awake until then. Either this is going out well one way or the other we will see... FUCK COMMIT MESSAGES! Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
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@ -207,6 +207,13 @@
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author = {Unknown Author},
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url = {https://www.nxp.com/docs/en/user-guide/UM10204.pdf}
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}
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@book{boehmer,
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year = {2009},
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month = Aug,
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title = {Elemente der angewandten Elektronik},
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publisher = {Viehweg},
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author = {Erwin Böhmer, Dietmar Erhardt, Wolfgang Oberschlep}
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}
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@Manual{ddc,
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year = {2007},
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month = Dec,
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BIN
main.pdf
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main.pdf
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1
main.tex
1
main.tex
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@ -190,6 +190,7 @@ geschlechtsunabh"angig verstanden werden soll.
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\allAuth\input{sections/Anhang/Projektterminplanung/projektterminplanung.tex}
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\allAuth\input{sections/Anhang/flash.tex}
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\DP\input{sections/Anhang/qualitaetssicherung.tex}
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\AB\subfile{sections/vhdl_intro/vhdl_intro.tex}
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\end{appendices}
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@ -63,11 +63,11 @@ Table \ref{tab:brauns_work} shows the times worked.
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\textbf{Date} & \textbf{Duration [h]} & \textbf{Task}\\
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\hline
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\hline
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2018-12-11 & 3 & Create Quartus project, implement first proof-of-concept design \\
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2018-12-11 & 3 & Cimplement first proof-of-concept design \\
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\hline
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2018-12-19 & 3 & ALU design and corresponding test bench \\
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\hline
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2019-01-18 & 5 & First processor prototype capable of running programs \\
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2019-01-18 & 5 & First processor prototype \\
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\hline
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2019-01-20 & 2 & Preliminary firmware build system \\
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\hline
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@ -109,7 +109,7 @@ Table \ref{tab:brauns_work} shows the times worked.
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\hline
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2019-03-04 & 1 & Misc bug fixes \\
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\hline
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2019-03-10 & 2 & Diagnose and fix interrupt related processor bug \\
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2019-03-10 & 2 & Fix interrupt related processor bug \\
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\hline
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2019-03-11 & 3 & CSR illegal instruction exceptions \\
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\hline
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@ -246,7 +246,7 @@ Table \ref{tab:brauns_work} shows the times worked.
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2020-03-31 & 4 & Documentation \\
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\hline
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\hline
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2020-04-01 & \textbf{SUM during school year} & 150h\\
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\multicolumn{2}{c}{\textbf{SUM during school year}} & 150h\\
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\hline
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\caption{Work time reference - Brauns}
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\label{tab:brauns_work}
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@ -38,7 +38,7 @@ Plank respectively.
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\textbf{Directory} & \textbf{Contents}\\
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\hline
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\hline
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code & Code sampkes written for this thesis\\
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code & Code samples written for this thesis\\
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\hline
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dipl & The source code for this thesis in \LaTeX\\
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\hline
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32
sections/Anhang/qualitaetssicherung.tex
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sections/Anhang/qualitaetssicherung.tex
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@ -0,0 +1,32 @@
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\section{Qualitätssicherung nach ISO-9003}
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Im zuge der Qualitätssicherung nach ISO-9003 wurden für die Hardwareperipherie
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laufend Messungen zur Funktionsprüfungen durchgeführt sowie für den Prozessor
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diverse Simulationsmodelle erstellt und verwendet. Der Messverlauf wurde
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beschrieben und die Messungen mit dem Soll-Wert verglichen. Zur Verifikation
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der in MS1 gesammelten PDF-Dateien wurde ein Shell-Skript verfasst, welches
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in Listing \ref{lst:mst-t1} eingesehen werden kann. Die Tests verifizieren nach
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dem Grobdesign welches in der Abgabe zu Meilenstein 1 auf dem dieser
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Diplomarbeit beigelegten Datenträger eingesehen werden kann.
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\begin{lstlisting}[language=bash,frame=trBL,
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breaklines=true, breakautoindent=true, formfeed=\newpage,
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label={lst:mst-t1},
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caption={Shell-Skript zum Testen der PDF-Dokumente},
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columns=flexible]
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#!/bin/bash
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for f in *.pdf; do
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echo "########################################"
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echo "Tesing $f..."
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echo "########################################" >> ./logfile
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if pdfinfo "$f" >> ./logfile; then
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echo "$f is correct!"
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else
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echo "$f is broken!"
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fi
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echo "########################################"
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done
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\end{lstlisting}
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@ -20,6 +20,9 @@ DAC was developed for audio aplications\cite{tlc7528}, which made its use
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obvious. The TLC-7528 was the only IC available as DIP
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\footnote{DIP... Dual Inline Package}, of which the pinout can be seen in Figure
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\ref{fig:tlc7528_pinout}.
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A R2R DAC is a dac which can sample very fast with very low internal noise due
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to the internal structure and low complexity.\cite{boehmer} These features are
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important for audio applications.
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\begin{figure}[H]
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\centering
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@ -93,3 +93,12 @@ attached. The blue modules below are the level shifters.
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\label{fig:fpga_mod}
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\end{figure}
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\subsubsection{Further work on the FPGA}
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One optional aim was for further examples to be developed for the FPGA which
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would interface with the hardware peripherals. These examples were partially
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developed and tested, though never recorded due to the currently ongoing
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COVID-19 crisis. These examples may be found inside the documentation of the
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processor part of this thesis or on the flash drive which comes with this
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thesis.
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@ -161,3 +161,38 @@ result the DAC and Serial Communication interface were chosen as peripherals.
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\caption{utility analysis results for peripherals}
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\label{tab:utility_result}
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\end{table}
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\subsubsection{Material and Infrastructure cost}
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The peripherals were mostly constructed with materials currently in stock at
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the Hackerspace Innsbruck. This limitation, while driving development time up,
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reduced the material cost significantly as resistors, capacitors and most
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standard logic ICs were in stock for the purpose of such projects. The materials
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which had to be ordered and were used in the final implementation of the
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peripherals are listed in Table \ref{tab:cost_hw}. Infrastructure usage at the
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Hackerspace is unlimted to anyone who is working on a project and a member of
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the community and free of charge.
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\begin{table}[H]
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\centering
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\resizebox{\textwidth}{!}{
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\begin{tabular}{ |l|c|c|}
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\hline
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\textbf{Name} & \textbf{Cost} & \textbf{Quantity}\\
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\hline
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\hline
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ADC 8bit RS-COMPONENTS & € 4.16 &3\\
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\hline
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8-bit D-Latch RS-COMPONENTS & € 2.21 &4\\
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\hline
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MAX232 RS-COMPONENTS & € 2.19 &2\\
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\hline
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Quartz, 1,8432 MHz POLLIN & € 0.15 &4\\
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\hline
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\hline
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\end{tabular}
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}
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\caption{List of ordered components and cost}
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\label{tab:cost_hw}
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\end{table}
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