Add information about external bus

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Xiretza 2020-03-27 12:50:24 +01:00
parent 244380ee5f
commit ad723217ad
Signed by: xiretza
GPG key ID: E51A6C6A1EB378ED

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@ -143,6 +143,12 @@ The exact timing differs between models, so all periods can be customized using
% TODO % TODO
\subsection{External Bus}
Bridging the internal SoC bus with the external peripheral bus requires a few steps. For one, the external data bus is bidirectional, so tri-state outputs must be used on the FPGA. In addition, the internal bus arbitrates components using addresses alone, while the external bus uses chip enable signals and overlapping address spaces.
Due to a mistake in the adapter board layout, the nibbles of the address and data buses are reversed (MSB to LSB are pins 7 to 0 on the FPGA, but 3 to 0 followed by 7 to 4 on the board). Thanks to the completely arbitrary mapping of FPGA pins, this can be mitigated without using any additional resources.
\section{Testing} \section{Testing}
\subsection{RISC-V Compliance Tests} \subsection{RISC-V Compliance Tests}