From ad723217add9667432956e9adb5bb08f1d9d5761 Mon Sep 17 00:00:00 2001
From: Xiretza <xiretza@xiretza.xyz>
Date: Fri, 27 Mar 2020 12:50:24 +0100
Subject: [PATCH] Add information about external bus

---
 sections/soc/soc.tex | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/sections/soc/soc.tex b/sections/soc/soc.tex
index d0e2194..2a7b7f9 100644
--- a/sections/soc/soc.tex
+++ b/sections/soc/soc.tex
@@ -143,6 +143,12 @@ The exact timing differs between models, so all periods can be customized using
 
 % TODO
 
+\subsection{External Bus}
+
+Bridging the internal SoC bus with the external peripheral bus requires a few steps. For one, the external data bus is bidirectional, so tri-state outputs must be used on the FPGA. In addition, the internal bus arbitrates components using addresses alone, while the external bus uses chip enable signals and overlapping address spaces.
+
+Due to a mistake in the adapter board layout, the nibbles of the address and data buses are reversed (MSB to LSB are pins 7 to 0 on the FPGA, but 3 to 0 followed by 7 to 4 on the board). Thanks to the completely arbitrary mapping of FPGA pins, this can be mitigated without using any additional resources.
+
 \section{Testing}
 
 \subsection{RISC-V Compliance Tests}