26 lines
377 B
VHDL
26 lines
377 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity flipflop is
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port (
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d : in std_logic;
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e : in std_logic;
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q : out std_logic;
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q_n : out std_logic
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);
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end entity;
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architecture rtl of flipflop is
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signal state : std_logic;
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begin
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store: process(e)
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begin
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if rising_edge(e) then
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state <= d;
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end if;
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end process;
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q <= state;
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q_n <= not state;
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end architecture;
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